encoder_time_post.vhd

8b10b design reference

  signal frame_out_MC_D : STD_LOGIC; 
  signal frame_out_MC_D1_PT_0 : STD_LOGIC; 
  signal frame_out_MC_D1 : STD_LOGIC; 
  signal frame_out_MC_D2 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_func_prs_state_ffd2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd2_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd1_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_prs_state_ffd1_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd3_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_prs_state_ffd1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_s_func_prs_state_ffd2_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_168_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_168_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_nds6_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_164_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_pds6_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_176_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_176_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_0_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_7_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_8_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_10_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_10_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_10_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_11_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_D2_PT_11_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_s_term_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_204_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_204_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_204_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_204_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_1_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_2_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_3_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_3_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_3_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_3_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_6_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_9_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_9_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_9_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_10_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_11_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_D2_PT_11_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_4_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_5_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_5_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_7_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_8_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_8_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_e_prel_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_6_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_6_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_d_prel_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_7_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_7_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_c_prel_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_8_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_8_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_enc_8b10b_b_prel_MC_D2_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_9_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_9_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_encoded_data_9_MC_D2_PT_1_IN5 : STD_LOGIC; 
begin
  dis_out_0 : X_BUF
    port map (
      I => dis_out_MC_Q,
      O => dis_out
    );
  dis_out_MC_Q_1 : X_BUF
    port map (
      I => dis_out_MC_Q_tsim_ireg_Q,
      O => dis_out_MC_Q
    );
  dis_out_MC_REG : X_BUF
    port map (
      I => dis_out_MC_D,
      O => dis_out_MC_Q_tsim_ireg_Q
    );
  dis_out_MC_D1_PT_0_2 : X_AND2
    port map (
      I0 => dis_in_II_UIM,
      I1 => dis_func_prs_state_ffd2,
      O => dis_out_MC_D1_PT_0
    );
  dis_out_MC_D1_3 : X_OR2
    port map (
      I0 => dis_out_MC_D1_PT_0,
      I1 => dis_out_MC_D1_PT_0,
      O => dis_out_MC_D1
    );
  dis_out_MC_D2_PT_0_4 : X_AND4
    port map (
      I0 => dis_in_II_UIM,
      I1 => dis_func_prs_state_ffd2,
      I2 => nds6,
      I3 => pds6,
      O => dis_out_MC_D2_PT_0
    );
  dis_out_MC_D2_PT_1_5 : X_AND4
    port map (
      I0 => dis_func_prs_state_ffd2,
      I1 => nds6,
      I2 => NlwInverterSignal_dis_out_MC_D2_PT_1_IN2,
      I3 => NlwInverterSignal_dis_out_MC_D2_PT_1_IN3,
      O => dis_out_MC_D2_PT_1
    );
  dis_out_MC_D2_PT_2_6 : X_AND4
    port map (
      I0 => dis_func_prs_state_ffd2,
      I1 => NlwInverterSignal_dis_out_MC_D2_PT_2_IN1,
      I2 => pds6,
      I3 => NlwInverterSignal_dis_out_MC_D2_PT_2_IN3,
      O => dis_out_MC_D2_PT_2
    );
  dis_out_MC_D2_PT_3_7 : X_AND4
    port map (
      I0 => dis_func_prs_state_ffd2,
      I1 => NlwInverterSignal_dis_out_MC_D2_PT_3_IN1,
      I2 => NlwInverterSignal_dis_out_MC_D2_PT_3_IN2,
      I3 => N_PZ_176,
      O => dis_out_MC_D2_PT_3
    );
  dis_out_MC_D2_8 : X_OR4
    port map (
      I0 => dis_out_MC_D2_PT_0,
      I1 => dis_out_MC_D2_PT_1,
      I2 => dis_out_MC_D2_PT_2,
      I3 => dis_out_MC_D2_PT_3,
      O => dis_out_MC_D2
    );
  dis_out_MC_XOR : X_XOR2
    port map (
      I0 => dis_out_MC_D1,
      I1 => dis_out_MC_D2,
      O => dis_out_MC_D
    );
  dis_in_II_UIM_9 : X_BUF
    port map (
      I => dis_in,
      O => dis_in_II_UIM
    );
  dis_func_prs_state_ffd2_10 : X_BUF
    port map (
      I => dis_func_prs_state_ffd2_MC_Q,
      O => dis_func_prs_state_ffd2
    );
  dis_func_prs_state_ffd2_MC_R_OR_PRLD_11 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => dis_func_prs_state_ffd2_MC_R_OR_PRLD
    );
  dis_func_prs_state_ffd2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dis_func_prs_state_ffd2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => dis_func_prs_state_ffd2_MC_R_OR_PRLD,
      O => dis_func_prs_state_ffd2_MC_Q
    );
  VCC_ONE : X_ONE
    port map (
      O => VCC
    );
  GND_ZERO : X_ZERO
    port map (
      O => GND
    );
  dis_func_prs_state_ffd2_MC_D1_12 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => dis_func_prs_state_ffd2_MC_D1
    );
  dis_func_prs_state_ffd2_MC_D2_PT_0_13 : X_AND2
    port map (
      I0 => dis_func_prs_state_ffd1,
      I1 => dis_func_prs_state_ffd1,
      O => dis_func_prs_state_ffd2_MC_D2_PT_0
    );
  dis_func_prs_state_ffd2_MC_D2_PT_1_14 : X_AND3
    port map (
      I0 => dis_func_prs_state_ffd2,
      I1 => NlwInverterSignal_dis_func_prs_state_ffd2_MC_D2_PT_1_IN1,
      I2 => prs_state_ffd1,
      O => dis_func_prs_state_ffd2_MC_D2_PT_1
    );
  dis_func_prs_state_ffd2_MC_D2_15 : X_OR2
    port map (
      I0 => dis_func_prs_state_ffd2_MC_D2_PT_0,
      I1 => dis_func_prs_state_ffd2_MC_D2_PT_1,
      O => dis_func_prs_state_ffd2_MC_D2
    );
  dis_func_prs_state_ffd2_MC_XOR : X_XOR2
    port map (
      I0 => dis_func_prs_state_ffd2_MC_D1,
      I1 => dis_func_prs_state_ffd2_MC_D2,
      O => dis_func_prs_state_ffd2_MC_D
    );
  dis_func_prs_state_ffd1_16 : X_BUF
    port map (
      I => dis_func_prs_state_ffd1_MC_Q,
      O => dis_func_prs_state_ffd1
    );
  dis_func_prs_state_ffd1_MC_R_OR_PRLD_17 : X_OR2
    port map (
      I0 => rst_II_FSR_Q,
      I1 => PRLD,
      O => dis_func_prs_state_ffd1_MC_R_OR_PRLD
    );
  dis_func_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dis_func_prs_state_ffd1_MC_D,
      CE => VCC,