poc1.rpt
来自「基于VHDL的POC编写与实现 实现三次握手」· RPT 代码 · 共 651 行 · 第 1/2 页
RPT
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Project Information d:\maxplus2_10\vhdl\poc1.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/04/2007 20:37:20
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
POC1
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
poc1 EPM7032LC44-6 15 10 0 22 2 68 %
User Pins: 15 10 0
Project Information d:\maxplus2_10\vhdl\poc1.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 37: File d:\maxplus2_10\vhdl\poc1.vhd: Found multiple assignments to the same signal or signal bit "IRQ" in a Process Statement -- only the last assignment will take effect
Warning: Line 34: File d:\maxplus2_10\vhdl\poc1.vhd: Found multiple assignments to the same signal or signal bit "SR7" in a Process Statement -- only the last assignment will take effect
Warning: Line 49: File d:\maxplus2_10\vhdl\poc1.vhd: Found multiple assignments to the same signal or signal bit "TR" in a Process Statement -- only the last assignment will take effect
Project Information d:\maxplus2_10\vhdl\poc1.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
Project Information d:\maxplus2_10\vhdl\poc1.rpt
** STATE MACHINE ASSIGNMENTS **
state: MACHINE
OF BITS (
state~2,
state~1
)
WITH STATES (
q0 = B"00",
q1 = B"11",
q2 = B"01"
);
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
***** Logic for device 'poc1' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
P P P V G G G C G R
D D D C N N N L N D C
2 0 3 C D D D K D Y S
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
PD1 | 7 39 | A0
RESERVED | 8 38 | PD7
D6 | 9 37 | PD6
GND | 10 36 | RW
D5 | 11 35 | VCC
D4 | 12 EPM7032LC44-6 34 | PD5
D3 | 13 33 | IRQ
A1 | 14 32 | D7
VCC | 15 31 | RESERVED
A2 | 16 30 | GND
D0 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
D D P T G V R R R R R
1 2 D R N C E E E E E
4 D C S S S S S
E E E E E
R R R R R
V V V V V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 6/16( 37%) 15/16( 93%) 5/16( 31%) 15/36( 41%)
B: LC17 - LC32 16/16(100%) 9/16( 56%) 6/16( 37%) 30/36( 83%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 24/32 ( 75%)
Total logic cells used: 22/32 ( 68%)
Total shareable expanders used: 2/32 ( 6%)
Total Turbo logic cells used: 22/32 ( 68%)
Total shareable expanders not available (n/a): 9/32 ( 28%)
Average fan-in: 8.72
Total fan-in: 192
Total input pins required: 15
Total output pins required: 10
Total bidirectional pins required: 0
Total logic cells required: 22
Total flipflops required: 22
Total product terms required: 88
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
39 (19) (B) INPUT 0 0 0 0 0 1 12 A0
14 (10) (A) INPUT 0 0 0 0 0 1 12 A1
16 (11) (A) INPUT 0 0 0 0 0 1 12 A2
43 - - INPUT G 0 0 0 0 0 0 0 CLK
40 (18) (B) INPUT 0 0 0 0 0 10 12 CS
17 (12) (A) INPUT 0 0 0 0 0 0 2 D0
18 (13) (A) INPUT 0 0 0 0 0 0 1 D1
19 (14) (A) INPUT 0 0 0 0 0 0 1 D2
13 (9) (A) INPUT 0 0 0 0 0 0 1 D3
12 (8) (A) INPUT 0 0 0 0 0 0 1 D4
11 (7) (A) INPUT 0 0 0 0 0 0 1 D5
9 (6) (A) INPUT 0 0 0 0 0 0 1 D6
32 (25) (B) INPUT 0 0 0 0 0 0 2 D7
41 (17) (B) INPUT 0 0 0 0 0 9 3 RDY
36 (22) (B) INPUT 0 0 0 0 0 1 12 RW
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 24 B FF + t 1 0 0 5 5 1 0 IRQ
5 2 A FF + t 1 0 1 2 4 1 0 PD0
7 4 A FF + t 1 0 1 2 4 1 0 PD1
6 3 A FF + t 1 0 1 2 4 1 0 PD2
4 1 A FF + t 1 0 1 2 4 1 0 PD3
20 15 A FF + t 1 0 1 2 4 1 0 PD4
34 23 B FF + t 1 0 1 2 4 1 0 PD5
37 21 B FF + t 1 0 1 2 4 1 0 PD6
38 20 B FF + t 1 0 1 2 4 1 0 PD7
21 16 A FF + t 0 0 0 2 3 1 0 TR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(29) 27 B DFFE + t 0 0 0 6 2 10 12 state~1
(28) 28 B DFFE + t 0 0 0 6 2 10 12 state~2
(41) 17 B DFFE + t 2 0 1 7 3 1 1 SR7 (:36)
(40) 18 B TFFE + t 0 0 0 6 3 1 1 SR0 (:43)
(25) 31 B TFFE + t 0 0 0 6 3 1 1 BR7 (:44)
(39) 19 B TFFE + t 0 0 0 6 3 1 1 BR6 (:45)
(24) 32 B TFFE + t 0 0 0 6 3 1 1 BR5 (:46)
(36) 22 B TFFE + t 0 0 0 6 3 1 1 BR4 (:47)
(32) 25 B TFFE + t 0 0 0 6 3 1 1 BR3 (:48)
(31) 26 B TFFE + t 0 0 0 6 3 1 1 BR2 (:49)
(27) 29 B TFFE + t 0 0 0 6 3 1 1 BR1 (:50)
(26) 30 B TFFE + t 0 0 0 6 3 1 1 BR0 (:51)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------- LC2 PD0
| +--------- LC4 PD1
| | +------- LC3 PD2
| | | +----- LC1 PD3
| | | | +--- LC15 PD4
| | | | | +- LC16 TR
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'A'
LC | | | | | | | A B | Logic cells that feed LAB 'A':
LC2 -> * - - - - - | * - | <-- PD0
LC4 -> - * - - - - | * - | <-- PD1
LC3 -> - - * - - - | * - | <-- PD2
LC1 -> - - - * - - | * - | <-- PD3
LC15 -> - - - - * - | * - | <-- PD4
LC16 -> - - - - - * | * - | <-- TR
Pin
43 -> - - - - - - | - - | <-- CLK
40 -> * * * * * * | * * | <-- CS
41 -> * * * * * * | * * | <-- RDY
LC27 -> * * * * * * | * * | <-- state~1
LC28 -> * * * * * * | * * | <-- state~2
LC22 -> - - - - * - | * * | <-- BR4
LC25 -> - - - * - - | * * | <-- BR3
LC26 -> - - * - - - | * * | <-- BR2
LC29 -> - * - - - - | * * | <-- BR1
LC30 -> * - - - - - | * * | <-- BR0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2_10\vhdl\poc1.rpt
poc1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC24 IRQ
| +----------------------------- LC23 PD5
| | +--------------------------- LC21 PD6
| | | +------------------------- LC20 PD7
| | | | +----------------------- LC27 state~1
| | | | | +--------------------- LC28 state~2
| | | | | | +------------------- LC17 SR7
| | | | | | | +----------------- LC18 SR0
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