poc.rpt

基于VHDL的POC编写与实现 实现三次握手

  _EQ016 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'nirq' 
-- Equation name is 'nirq', location is LC059, type is output.
 nirq    = LCELL( _EQ017 $  VCC);
  _EQ017 =  psr0 &  psr7;

-- Node name is 'pd0' = ':31' 
-- Equation name is 'pd0', type is output 
 pd0     = TFFE( _EQ018, GLOBAL(!clk),  VCC,  VCC,  _EQ019);
  _EQ018 =  br0 & !pd0 & !rdy &  rw & !state~1 &  state~2
         # !br0 &  pd0 & !rdy &  rw & !state~1 &  state~2;
  _EQ019 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd1' = ':29' 
-- Equation name is 'pd1', type is output 
 pd1     = TFFE( _EQ020, GLOBAL(!clk),  VCC,  VCC,  _EQ021);
  _EQ020 =  br1 & !pd1 & !rdy &  rw & !state~1 &  state~2
         # !br1 &  pd1 & !rdy &  rw & !state~1 &  state~2;
  _EQ021 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd2' = ':27' 
-- Equation name is 'pd2', type is output 
 pd2     = TFFE( _EQ022, GLOBAL(!clk),  VCC,  VCC,  _EQ023);
  _EQ022 =  br2 & !pd2 & !rdy &  rw & !state~1 &  state~2
         # !br2 &  pd2 & !rdy &  rw & !state~1 &  state~2;
  _EQ023 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd3' = ':25' 
-- Equation name is 'pd3', type is output 
 pd3     = TFFE( _EQ024, GLOBAL(!clk),  VCC,  VCC,  _EQ025);
  _EQ024 =  br3 & !pd3 & !rdy &  rw & !state~1 &  state~2
         # !br3 &  pd3 & !rdy &  rw & !state~1 &  state~2;
  _EQ025 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd4' = ':23' 
-- Equation name is 'pd4', type is output 
 pd4     = TFFE( _EQ026, GLOBAL(!clk),  VCC,  VCC,  _EQ027);
  _EQ026 =  br4 & !pd4 & !rdy &  rw & !state~1 &  state~2
         # !br4 &  pd4 & !rdy &  rw & !state~1 &  state~2;
  _EQ027 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd5' = ':21' 
-- Equation name is 'pd5', type is output 
 pd5     = TFFE( _EQ028, GLOBAL(!clk),  VCC,  VCC,  _EQ029);
  _EQ028 =  br5 & !pd5 & !rdy &  rw & !state~1 &  state~2
         # !br5 &  pd5 & !rdy &  rw & !state~1 &  state~2;
  _EQ029 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd6' = ':19' 
-- Equation name is 'pd6', type is output 
 pd6     = TFFE( _EQ030, GLOBAL(!clk),  VCC,  VCC,  _EQ031);
  _EQ030 =  br6 & !pd6 & !rdy &  rw & !state~1 &  state~2
         # !br6 &  pd6 & !rdy &  rw & !state~1 &  state~2;
  _EQ031 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'pd7' = ':17' 
-- Equation name is 'pd7', type is output 
 pd7     = TFFE( _EQ032, GLOBAL(!clk),  VCC,  VCC,  _EQ033);
  _EQ032 =  br7 & !pd7 & !rdy &  rw & !state~1 &  state~2
         # !br7 &  pd7 & !rdy &  rw & !state~1 &  state~2;
  _EQ033 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr0' = 'sr0' 
-- Equation name is 'psr0', location is LC064, type is output.
 psr0    = TFFE( _EQ034, GLOBAL(!clk),  VCC,  VCC,  _EQ035);
  _EQ034 = !a0 & !a1 & !a2 &  d0 & !psr0 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d0 &  psr0 & !state~1 & !state~2;
  _EQ035 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr1' = 'sr1' 
-- Equation name is 'psr1', location is LC039, type is output.
 psr1    = TFFE( _EQ036, GLOBAL(!clk),  VCC,  VCC,  _EQ037);
  _EQ036 = !a0 & !a1 & !a2 &  d1 & !psr1 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d1 &  psr1 & !state~1 & !state~2;
  _EQ037 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr2' = 'sr2' 
-- Equation name is 'psr2', location is LC033, type is output.
 psr2    = TFFE( _EQ038, GLOBAL(!clk),  VCC,  VCC,  _EQ039);
  _EQ038 = !a0 & !a1 & !a2 &  d2 & !psr2 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d2 &  psr2 & !state~1 & !state~2;
  _EQ039 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr3' = 'sr3' 
-- Equation name is 'psr3', location is LC035, type is output.
 psr3    = TFFE( _EQ040, GLOBAL(!clk),  VCC,  VCC,  _EQ041);
  _EQ040 = !a0 & !a1 & !a2 &  d3 & !psr3 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d3 &  psr3 & !state~1 & !state~2;
  _EQ041 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr4' = 'sr4' 
-- Equation name is 'psr4', location is LC036, type is output.
 psr4    = TFFE( _EQ042, GLOBAL(!clk),  VCC,  VCC,  _EQ043);
  _EQ042 = !a0 & !a1 & !a2 &  d4 & !psr4 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d4 &  psr4 & !state~1 & !state~2;
  _EQ043 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr5' = 'sr5' 
-- Equation name is 'psr5', location is LC037, type is output.
 psr5    = TFFE( _EQ044, GLOBAL(!clk),  VCC,  VCC,  _EQ045);
  _EQ044 = !a0 & !a1 & !a2 &  d5 & !psr5 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d5 &  psr5 & !state~1 & !state~2;
  _EQ045 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr6' = 'sr6' 
-- Equation name is 'psr6', location is LC057, type is output.
 psr6    = TFFE( _EQ046, GLOBAL(!clk),  VCC,  VCC,  _EQ047);
  _EQ046 = !a0 & !a1 & !a2 &  d6 & !psr6 & !state~1 & !state~2
         # !a0 & !a1 & !a2 & !d6 &  psr6 & !state~1 & !state~2;
  _EQ047 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'psr7' = 'sr7' 
-- Equation name is 'psr7', location is LC049, type is output.
 psr7    = TFFE( _EQ048, GLOBAL(!clk),  VCC,  VCC,  _EQ049);
  _EQ048 = !a0 & !a1 & !a2 &  d7 & !psr7 & !state~1 & !state~2
         #  a0 & !a1 & !a2 &  psr7 & !state~1 & !state~2
         # !a1 & !a2 & !d7 &  psr7 & !state~1 & !state~2
         # !psr7 &  rdy &  state~1;
  _EQ049 =  _X001;
  _X001  = EXP( cs &  reset);

-- Node name is 'state~1' 
-- Equation name is 'state~1', location is LC056, type is buried.
state~1  = DFFE( _EQ050 $  GND, GLOBAL(!clk), !_EQ051,  VCC,  VCC);
  _EQ050 = !rdy & !reset &  rw & !state~1 &  state~2
         # !cs & !rdy &  rw & !state~1 &  state~2
         # !rdy & !reset &  state~1 & !state~2
         # !cs & !rdy &  state~1 & !state~2;
  _EQ051 =  cs &  reset;

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC050, type is buried.
state~2  = DFFE( _EQ052 $  _EQ053, GLOBAL(!clk), !_EQ054,  VCC,  VCC);
  _EQ052 = !a0 & !a1 & !a2 & !state~1 & !state~2 &  _X002
         # !rdy &  rw & !state~1 &  state~2 &  _X002
         #  cs &  reset & !state~1 &  _X002;
  _X002  = EXP( psr7 & !state~2);
  _EQ053 = !state~1 &  _X002;
  _X002  = EXP( psr7 & !state~2);
  _EQ054 =  cs &  reset;

-- Node name is 'tr' = ':33' 
-- Equation name is 'tr', type is output 
 tr      = TFFE( _EQ055, GLOBAL(!clk),  VCC,  VCC,  _EQ056);
  _EQ055 = !rdy &  rw & !state~1 &  state~2 &  tr
         #  a2 & !psr7 & !state~1 & !state~2 & !tr
         #  a1 & !psr7 & !state~1 & !state~2 & !tr
         #  a0 & !psr7 & !state~1 & !state~2 & !tr;
  _EQ056 =  _X001;
  _X001  = EXP( cs &  reset);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs B, C, D




Project Information                                d:\maxplus2_10\vhdl\poc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000AE' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,082K