poc1.vhd

来自「基于VHDL的POC编写与实现 实现三次握手」· VHDL 代码 · 共 69 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity poc1 is
  port( CLK:        in std_logic;
        CS:         in std_logic;
        RW:         in std_logic;                
        A:          in std_logic_vector(2 downto 0); 
        D:          in std_logic_vector(7 downto 0); 
        RDY :       in std_logic;  
        PD:         out std_logic_vector(7 downto 0); 
        IRQ:        out std_logic;  
        TR:         out std_logic        );
end poc1;
        
architecture arc_poc of poc1 is
  type state_type is (q0,q1,q2);
  signal state: state_type; 
  signal SR: std_logic_vector(7 downto 0); 
  signal BR: std_logic_vector(7 downto 0); 
  begin 
  
  process(clk)
     begin
     if cs='0'  then
           TR<='0';
           SR<="10000000";
           state<=q0;
      elsif clk'event and clk='1' then          
       case state is

        when q0 => ---input the data to SR and BR    
            if RW='1' and A="000" then ---input the data to SR
                   SR<=D; 
                end if;
            if SR(0)='1' and SR(7)='1' then ---judge the interrupt
                IRQ<='1';
             else IRQ<='0';
             end if;          
              if RW='1' and A="001"  then   ---input the data to BR
                 BR<=D;
                 IRQ<='0';
                 SR(7)<='0';  ---ready flag bit
                 state<=q1;
                end if;   
       
        when q1=>   --wait untill the printer is ready
           if  RDY='1'  then  --printer is ready ,output the transfer request
                TR<='1';
                 end if;
            if RDY='0' then   --untill printer begins to print,clear the transfer request
               TR<='0'; 
               state<=q2;              
              end if;
                                 
        when q2=>  --printing
           if RDY='0'  then   -- transfering is not over 
                 PD<=BR; 
                 state<=q2;   
             else   
                 SR(7)<='1';  --transfering is over,the poc is ready
                 state<=q0;
           end if;         
       end case;
     end if;
     end process;
    end arc_poc;