poc.rpt

基于VHDL的POC编写与实现 实现三次握手

-- Node name is 'pd1' 
-- Equation name is 'pd1', type is output 
pd1      =  _LC8_D8;

-- Node name is 'pd2' 
-- Equation name is 'pd2', type is output 
pd2      =  _LC6_D8;

-- Node name is 'pd3' 
-- Equation name is 'pd3', type is output 
pd3      =  _LC5_D8;

-- Node name is 'pd4' 
-- Equation name is 'pd4', type is output 
pd4      =  _LC8_E7;

-- Node name is 'pd5' 
-- Equation name is 'pd5', type is output 
pd5      =  _LC7_E7;

-- Node name is 'pd6' 
-- Equation name is 'pd6', type is output 
pd6      =  _LC4_E7;

-- Node name is 'pd7' 
-- Equation name is 'pd7', type is output 
pd7      =  _LC3_E7;

-- Node name is ':36' = 'sr7' 
-- Equation name is 'sr7', location is LC5_A5, type is buried.
!sr7     = sr7~NOT;
sr7~NOT  = DFFE( _EQ009, GLOBAL(!clk), !_LC1_C12,  VCC,  VCC);
  _EQ009 = !_LC4_A5 &  state~3
         # !d7 & !state~3
         # !d7 & !_LC4_A5
         #  _LC2_A9 & !state~3
         #  _LC2_A9 & !_LC4_A5;

-- Node name is 'state~1' 
-- Equation name is 'state~1', location is LC3_A5, type is buried.
state~1  = DFFE( _EQ010, GLOBAL(!clk), !_LC1_C12,  VCC,  VCC);
  _EQ010 = !rdy &  state~1
         # !rdy &  state~2;

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC2_A5, type is buried.
state~2  = DFFE( _EQ011, GLOBAL(!clk), !_LC1_C12,  VCC,  VCC);
  _EQ011 = !sr7 & !state~3
         #  rdy &  state~2;

-- Node name is 'state~3' 
-- Equation name is 'state~3', location is LC6_A5, type is buried.
state~3  = DFFE( _EQ012, GLOBAL(!clk), !_LC1_C12,  VCC,  VCC);
  _EQ012 = !state~1 &  state~3
         # !sr7 & !state~1
         # !rdy &  state~3
         # !rdy & !sr7;

-- Node name is 'tr' 
-- Equation name is 'tr', type is bidir 
tr       = TRI(_LC8_A5,  VCC);

-- Node name is ':17' 
-- Equation name is '_LC3_E7', type is buried 
_LC3_E7  = DFFE( _EQ013, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ013 =  br7 & !_LC1_A5
         #  _LC1_A5 &  _LC3_E7;

-- Node name is ':19' 
-- Equation name is '_LC4_E7', type is buried 
_LC4_E7  = DFFE( _EQ014, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ014 =  br6 & !_LC1_A5
         #  _LC1_A5 &  _LC4_E7;

-- Node name is ':21' 
-- Equation name is '_LC7_E7', type is buried 
_LC7_E7  = DFFE( _EQ015, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ015 =  br5 & !_LC1_A5
         #  _LC1_A5 &  _LC7_E7;

-- Node name is ':23' 
-- Equation name is '_LC8_E7', type is buried 
_LC8_E7  = DFFE( _EQ016, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ016 =  br4 & !_LC1_A5
         #  _LC1_A5 &  _LC8_E7;

-- Node name is ':25' 
-- Equation name is '_LC5_D8', type is buried 
_LC5_D8  = DFFE( _EQ017, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ017 =  br3 & !_LC1_A5
         #  _LC1_A5 &  _LC5_D8;

-- Node name is ':27' 
-- Equation name is '_LC6_D8', type is buried 
_LC6_D8  = DFFE( _EQ018, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ018 =  br2 & !_LC1_A5
         #  _LC1_A5 &  _LC6_D8;

-- Node name is ':29' 
-- Equation name is '_LC8_D8', type is buried 
_LC8_D8  = DFFE( _EQ019, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ019 =  br1 & !_LC1_A5
         #  _LC1_A5 &  _LC8_D8;

-- Node name is ':31' 
-- Equation name is '_LC2_D8', type is buried 
_LC2_D8  = DFFE( _EQ020, GLOBAL(!clk),  VCC,  VCC, !_LC1_C12);
  _EQ020 =  br0 & !_LC1_A5
         #  _LC1_A5 &  _LC2_D8;

-- Node name is ':33' 
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = DFFE( _EQ021, GLOBAL(!clk), !_LC1_C12,  VCC,  VCC);
  _EQ021 = !sr7 & !state~3
         # !state~3 &  tr
         #  _LC7_A5 &  tr;

-- Node name is ':102' 
-- Equation name is '_LC1_C12', type is buried 
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ022);
  _EQ022 = !reset
         # !cs;

-- Node name is ':138' 
-- Equation name is '_LC2_A9', type is buried 
_LC2_A9  = LCELL( _EQ023);
  _EQ023 = !a0 & !a1 & !a2;

-- Node name is '~662~1' 
-- Equation name is '~662~1', location is LC1_A5, type is buried.
-- synthesized logic cell 
_LC1_A5  = LCELL( _EQ024);
  _EQ024 = !rw
         # !state~2
         # !state~3;

-- Node name is '~734~1' 
-- Equation name is '~734~1', location is LC1_A9, type is buried.
-- synthesized logic cell 
!_LC1_A9 = _LC1_A9~NOT;
_LC1_A9~NOT = LCELL( _EQ025);
  _EQ025 = !a0 & !a1 & !a2 & !state~3;

-- Node name is '~743~1' 
-- Equation name is '~743~1', location is LC4_A5, type is buried.
-- synthesized logic cell 
!_LC4_A5 = _LC4_A5~NOT;
_LC4_A5~NOT = LCELL( _EQ026);
  _EQ026 = !rdy & !sr7
         # !sr7 &  state~2;

-- Node name is '~815~1' 
-- Equation name is '~815~1', location is LC7_A5, type is buried.
-- synthesized logic cell 
_LC7_A5  = LCELL( _EQ027);
  _EQ027 =  rdy
         # !state~2;



Project Information                                             d:\new\poc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,990K