📄 poc.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\new\poc.rpt
poc
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
101 - - A -- OUTPUT 0 1 0 0 nirq
91 - - D -- OUTPUT 0 1 0 0 pd0
88 - - D -- OUTPUT 0 1 0 0 pd1
89 - - D -- OUTPUT 0 1 0 0 pd2
90 - - D -- OUTPUT 0 1 0 0 pd3
83 - - E -- OUTPUT 0 1 0 0 pd4
29 - - E -- OUTPUT 0 1 0 0 pd5
86 - - E -- OUTPUT 0 1 0 0 pd6
27 - - E -- OUTPUT 0 1 0 0 pd7
100 - - A -- TRI 0 1 0 1 tr
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\new\poc.rpt
poc
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 05 DFFE + 1 2 0 1 state~1
- 2 - A 05 DFFE + 1 3 0 4 state~2
- 6 - A 05 DFFE + 1 3 1 5 state~3
- 3 - E 07 DFFE + 0 3 1 0 :17
- 4 - E 07 DFFE + 0 3 1 0 :19
- 7 - E 07 DFFE + 0 3 1 0 :21
- 8 - E 07 DFFE + 0 3 1 0 :23
- 5 - D 08 DFFE + 0 3 1 0 :25
- 6 - D 08 DFFE + 0 3 1 0 :27
- 8 - D 08 DFFE + 0 3 1 0 :29
- 2 - D 08 DFFE + 0 3 1 0 :31
- 8 - A 05 DFFE + 0 5 1 0 :33
- 5 - A 05 DFFE + ! 1 4 0 4 sr7 (:36)
- 6 - E 07 DFFE + 1 2 0 1 br7 (:44)
- 5 - E 07 DFFE + 1 2 0 1 br6 (:45)
- 2 - E 07 DFFE + 1 2 0 1 br5 (:46)
- 1 - E 07 DFFE + 1 2 0 1 br4 (:47)
- 7 - D 08 DFFE + 1 2 0 1 br3 (:48)
- 4 - D 08 DFFE + 1 2 0 1 br2 (:49)
- 3 - D 08 DFFE + 1 2 0 1 br1 (:50)
- 1 - D 08 DFFE + 1 2 0 1 br0 (:51)
- 1 - C 12 OR2 ! 2 0 0 21 :102
- 2 - A 09 AND2 3 0 0 1 :138
- 1 - A 05 OR2 s 1 2 0 8 ~662~1
- 1 - A 09 AND2 s ! 3 1 0 8 ~734~1
- 4 - A 05 OR2 s ! 1 2 0 1 ~743~1
- 7 - A 05 OR2 s 1 1 0 1 ~815~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\new\poc.rpt
poc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/144( 2%) 4/ 72( 5%) 0/ 72( 0%) 1/16( 6%) 1/16( 6%) 1/16( 6%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
D: 6/144( 4%) 5/ 72( 6%) 0/ 72( 0%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
E: 7/144( 4%) 3/ 72( 4%) 0/ 72( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\new\poc.rpt
poc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 21 clk
Device-Specific Information: d:\new\poc.rpt
poc
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 21 :102
Device-Specific Information: d:\new\poc.rpt
poc
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
clk : INPUT;
cs : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
rdy : INPUT;
reset : INPUT;
rw : INPUT;
-- Node name is ':51' = 'br0'
-- Equation name is 'br0', location is LC1_D8, type is buried.
br0 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ001 = br0 & _LC1_A9
# d0 & !_LC1_A9;
-- Node name is ':50' = 'br1'
-- Equation name is 'br1', location is LC3_D8, type is buried.
br1 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ002 = br1 & _LC1_A9
# d1 & !_LC1_A9;
-- Node name is ':49' = 'br2'
-- Equation name is 'br2', location is LC4_D8, type is buried.
br2 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ003 = br2 & _LC1_A9
# d2 & !_LC1_A9;
-- Node name is ':48' = 'br3'
-- Equation name is 'br3', location is LC7_D8, type is buried.
br3 = DFFE( _EQ004, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ004 = br3 & _LC1_A9
# d3 & !_LC1_A9;
-- Node name is ':47' = 'br4'
-- Equation name is 'br4', location is LC1_E7, type is buried.
br4 = DFFE( _EQ005, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ005 = br4 & _LC1_A9
# d4 & !_LC1_A9;
-- Node name is ':46' = 'br5'
-- Equation name is 'br5', location is LC2_E7, type is buried.
br5 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ006 = br5 & _LC1_A9
# d5 & !_LC1_A9;
-- Node name is ':45' = 'br6'
-- Equation name is 'br6', location is LC5_E7, type is buried.
br6 = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ007 = br6 & _LC1_A9
# d6 & !_LC1_A9;
-- Node name is ':44' = 'br7'
-- Equation name is 'br7', location is LC6_E7, type is buried.
br7 = DFFE( _EQ008, GLOBAL(!clk), VCC, VCC, !_LC1_C12);
_EQ008 = br7 & _LC1_A9
# d7 & !_LC1_A9;
-- Node name is 'nirq'
-- Equation name is 'nirq', type is output
nirq = state~3;
-- Node name is 'pd0'
-- Equation name is 'pd0', type is output
pd0 = _LC2_D8;
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