printer.rpt

poc的VHDL详细设计 实现握手信号的交互

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                f:\poc\printer.rpt
printer

** BURIED LOGIC **

                                               Shareable
                                               Expanders     Fan-In    Fan-Out
 IOC     LC   Row  Col  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK Name
   -      9    B    01        OR2      t        0      0   0    2    5    1    1  :11
   -      1    B    01      NAND2      t !      0      0   0    1    1    0    5  :18
   -      2    B    01       TFFE      t        1      0   0    2    4    0    1  |74193:20|QD (|74193:20|:23)
   -      3    B    01       TFFE      t        1      0   0    2    3    0    2  |74193:20|QC (|74193:20|:24)
   -      4    B    01       TFFE      t        1      0   0    2    2    0    3  |74193:20|QB (|74193:20|:25)
   -      5    B    01       TFFE      t        1      0   0    2    1    0    4  |74193:20|QA (|74193:20|:26)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                                f:\poc\printer.rpt
printer

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

         FastTrack                                 
Row     Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       4/ 96(  4%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
C:       0/ 96(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:       0/ 96(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/48(  0%)     0/20(  0%)      0/20(  0%)       0/20(  0%)
02:      0/48(  0%)     0/20(  0%)      0/20(  0%)       0/20(  0%)
03:      0/48(  0%)     0/20(  0%)      0/20(  0%)       0/20(  0%)
04:      0/48(  0%)     0/20(  0%)      0/20(  0%)       0/20(  0%)
05:      0/48(  0%)     0/20(  0%)      0/20(  0%)       0/20(  0%)


Device-Specific Information:                                f:\poc\printer.rpt
printer

** EQUATIONS **

clk      : INPUT;
reset    : INPUT;
tr       : INPUT;

-- Node name is 'rdy' 
-- Equation name is 'rdy', type is output 
rdy      =  _LC9_B1;

-- Node name is '|74193:20|:26' = '|74193:20|QA' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = TFFE( VCC,  _EQ001,  VCC, !tr,  VCC);
  _EQ001 =  _X001;
  _X001  = EXP( clk &  _LC1_B1);

-- Node name is '|74193:20|:25' = '|74193:20|QB' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = TFFE( VCC,  _EQ002, !tr,  VCC,  VCC);
  _EQ002 =  _X002;
  _X002  = EXP( clk &  _LC1_B1 & !_LC5_B1);

-- Node name is '|74193:20|:24' = '|74193:20|QC' 
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = TFFE( VCC,  _EQ003,  VCC, !tr,  VCC);
  _EQ003 =  _X003;
  _X003  = EXP( clk &  _LC1_B1 & !_LC4_B1 & !_LC5_B1);

-- Node name is '|74193:20|:23' = '|74193:20|QD' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = TFFE( VCC,  _EQ004, !tr,  VCC,  VCC);
  _EQ004 =  _X004;
  _X004  = EXP( clk &  _LC1_B1 & !_LC3_B1 & !_LC4_B1 & !_LC5_B1);

-- Node name is ':11' 
-- Equation name is '_LC9_B1', type is buried 
_LC9_B1  = LCELL( _EQ005 $  GND);
  _EQ005 =  clk & !_LC2_B1 & !_LC3_B1 & !_LC4_B1 & !_LC5_B1
         # !reset
         # !_LC1_B1;

-- Node name is ':18' 
-- Equation name is '_LC1_B1', type is buried 
!_LC1_B1 = _LC1_B1~NOT;
_LC1_B1~NOT = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC9_B1 & !tr;



Project Information                                         f:\poc\printer.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX9000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,559K