📄 poc.rpt
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Device-Specific Information: f:\poc\poc.rpt
poc
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(B7) 56 D DFFE + t 1 0 1 4 2 17 10 state~1
- 50 D DFFE + t 2 0 1 7 3 17 10 state~2
- 63 D TFFE + t 1 1 0 6 4 1 1 br7 (:52)
- 58 D TFFE + t 1 1 0 6 4 1 1 br6 (:53)
- 60 D TFFE + t 1 1 0 6 4 1 1 br5 (:54)
- 61 D TFFE + t 1 1 0 6 4 1 1 br4 (:55)
- 54 D TFFE + t 1 1 0 6 4 1 1 br3 (:56)
- 34 C TFFE + t 1 1 0 6 4 1 1 br2 (:57)
- 38 C TFFE + t 1 1 0 6 4 1 1 br1 (:58)
- 55 D TFFE + t 1 1 0 6 4 1 1 br0 (:59)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: f:\poc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC25 pd0
| +- LC30 pd3
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D | Logic cells that feed LAB 'B':
LC25 -> * - | - * - - | <-- pd0
LC30 -> - * | - * - - | <-- pd3
Pin
A5 -> - - | - - - - | <-- clk
D2 -> * * | - * * * | <-- cs
C1 -> * * | - * * * | <-- rdy
D4 -> * * | - * * * | <-- reset
D1 -> * * | - * * * | <-- rw
LC56 -> * * | - * * * | <-- state~1
LC50 -> * * | - * * * | <-- state~2
LC54 -> - * | - * - * | <-- br3
LC55 -> * - | - * - * | <-- br0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\poc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------- LC41 pd1
| +----------------- LC46 pd2
| | +--------------- LC39 psr1
| | | +------------- LC33 psr2
| | | | +----------- LC35 psr3
| | | | | +--------- LC36 psr4
| | | | | | +------- LC37 psr5
| | | | | | | +----- LC40 tr
| | | | | | | | +--- LC34 br2
| | | | | | | | | +- LC38 br1
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC41 -> * - - - - - - - - - | - - * - | <-- pd1
LC46 -> - * - - - - - - - - | - - * - | <-- pd2
LC39 -> - - * - - - - - - - | - - * - | <-- psr1
LC33 -> - - - * - - - - - - | - - * - | <-- psr2
LC35 -> - - - - * - - - - - | - - * - | <-- psr3
LC36 -> - - - - - * - - - - | - - * - | <-- psr4
LC37 -> - - - - - - * - - - | - - * - | <-- psr5
LC40 -> - - - - - - - * - - | - - * - | <-- tr
LC34 -> - * - - - - - - * - | - - * - | <-- br2
LC38 -> * - - - - - - - - * | - - * - | <-- br1
Pin
B2 -> - - * * * * * * * * | - - * * | <-- a0
G4 -> - - * * * * * * * * | - - * * | <-- a1
A2 -> - - * * * * * * * * | - - * * | <-- a2
A5 -> - - - - - - - - - - | - - - - | <-- clk
D2 -> * * * * * * * * * * | - * * * | <-- cs
G1 -> - - * - - - - - - * | - - * - | <-- d1
F3 -> - - - * - - - - * - | - - * - | <-- d2
C3 -> - - - - * - - - - - | - - * * | <-- d3
E3 -> - - - - - * - - - - | - - * * | <-- d4
A1 -> - - - - - - * - - - | - - * * | <-- d5
C1 -> * * - - - - - * - - | - * * * | <-- rdy
D4 -> * * * * * * * * * * | - * * * | <-- reset
D1 -> * * - - - - - * - - | - * * * | <-- rw
LC49 -> - - - - - - - * * * | - - * * | <-- psr7
LC56 -> * * * * * * * * * * | - * * * | <-- state~1
LC50 -> * * * * * * * * * * | - * * * | <-- state~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\poc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC59 nirq
| +----------------------------- LC53 pd4
| | +--------------------------- LC52 pd5
| | | +------------------------- LC51 pd6
| | | | +----------------------- LC62 pd7
| | | | | +--------------------- LC64 psr0
| | | | | | +------------------- LC57 psr6
| | | | | | | +----------------- LC49 psr7
| | | | | | | | +--------------- LC56 state~1
| | | | | | | | | +------------- LC50 state~2
| | | | | | | | | | +----------- LC63 br7
| | | | | | | | | | | +--------- LC58 br6
| | | | | | | | | | | | +------- LC60 br5
| | | | | | | | | | | | | +----- LC61 br4
| | | | | | | | | | | | | | +--- LC54 br3
| | | | | | | | | | | | | | | +- LC55 br0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC53 -> - * - - - - - - - - - - - - - - | - - - * | <-- pd4
LC52 -> - - * - - - - - - - - - - - - - | - - - * | <-- pd5
LC51 -> - - - * - - - - - - - - - - - - | - - - * | <-- pd6
LC62 -> - - - - * - - - - - - - - - - - | - - - * | <-- pd7
LC64 -> * - - - - * - - - - - - - - - - | - - - * | <-- psr0
LC57 -> - - - - - - * - - - - - - - - - | - - - * | <-- psr6
LC49 -> * - - - - - - * - * * * * * * * | - - * * | <-- psr7
LC56 -> - * * * * * * * * * * * * * * * | - * * * | <-- state~1
LC50 -> - * * * * * * * * * * * * * * * | - * * * | <-- state~2
LC63 -> - - - - * - - - - - * - - - - - | - - - * | <-- br7
LC58 -> - - - * - - - - - - - * - - - - | - - - * | <-- br6
LC60 -> - - * - - - - - - - - - * - - - | - - - * | <-- br5
LC61 -> - * - - - - - - - - - - - * - - | - - - * | <-- br4
LC54 -> - - - - - - - - - - - - - - * - | - * - * | <-- br3
LC55 -> - - - - - - - - - - - - - - - * | - * - * | <-- br0
Pin
B2 -> - - - - - * * * - * * * * * * * | - - * * | <-- a0
G4 -> - - - - - * * * - * * * * * * * | - - * * | <-- a1
A2 -> - - - - - * * * - * * * * * * * | - - * * | <-- a2
A5 -> - - - - - - - - - - - - - - - - | - - - - | <-- clk
D2 -> - * * * * * * * * * * * * * * * | - * * * | <-- cs
G3 -> - - - - - * - - - - - - - - - * | - - - * | <-- d0
C3 -> - - - - - - - - - - - - - - * - | - - * * | <-- d3
E3 -> - - - - - - - - - - - - - * - - | - - * * | <-- d4
A1 -> - - - - - - - - - - - - * - - - | - - * * | <-- d5
G2 -> - - - - - - * - - - - * - - - - | - - - * | <-- d6
F2 -> - - - - - - - * - - * - - - - - | - - - * | <-- d7
C1 -> - * * * * - - * * * - - - - - - | - * * * | <-- rdy
D4 -> - * * * * * * * * * * * * * * * | - * * * | <-- reset
D1 -> - * * * * - - - * * - - - - - - | - * * * | <-- rw
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\poc\poc.rpt
poc
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
clk : INPUT;
cs : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
rdy : INPUT;
reset : INPUT;
rw : INPUT;
-- Node name is ':59' = 'br0'
-- Equation name is 'br0', location is LC055, type is buried.
br0 = TFFE( _EQ001, GLOBAL( clk), VCC, VCC, _EQ002);
_EQ001 = a0 & !a1 & !a2 & !br0 & d0 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br0 & !d0 & psr7 & !state~1 & !state~2;
_EQ002 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':58' = 'br1'
-- Equation name is 'br1', location is LC038, type is buried.
br1 = TFFE( _EQ003, GLOBAL( clk), VCC, VCC, _EQ004);
_EQ003 = a0 & !a1 & !a2 & !br1 & d1 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br1 & !d1 & psr7 & !state~1 & !state~2;
_EQ004 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':57' = 'br2'
-- Equation name is 'br2', location is LC034, type is buried.
br2 = TFFE( _EQ005, GLOBAL( clk), VCC, VCC, _EQ006);
_EQ005 = a0 & !a1 & !a2 & !br2 & d2 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br2 & !d2 & psr7 & !state~1 & !state~2;
_EQ006 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':56' = 'br3'
-- Equation name is 'br3', location is LC054, type is buried.
br3 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, _EQ008);
_EQ007 = a0 & !a1 & !a2 & !br3 & d3 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br3 & !d3 & psr7 & !state~1 & !state~2;
_EQ008 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':55' = 'br4'
-- Equation name is 'br4', location is LC061, type is buried.
br4 = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, _EQ010);
_EQ009 = a0 & !a1 & !a2 & !br4 & d4 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br4 & !d4 & psr7 & !state~1 & !state~2;
_EQ010 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':54' = 'br5'
-- Equation name is 'br5', location is LC060, type is buried.
br5 = TFFE( _EQ011, GLOBAL( clk), VCC, VCC, _EQ012);
_EQ011 = a0 & !a1 & !a2 & !br5 & d5 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br5 & !d5 & psr7 & !state~1 & !state~2;
_EQ012 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':53' = 'br6'
-- Equation name is 'br6', location is LC058, type is buried.
br6 = TFFE( _EQ013, GLOBAL( clk), VCC, VCC, _EQ014);
_EQ013 = a0 & !a1 & !a2 & !br6 & d6 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br6 & !d6 & psr7 & !state~1 & !state~2;
_EQ014 = _X001;
_X001 = EXP( cs & reset);
-- Node name is ':52' = 'br7'
-- Equation name is 'br7', location is LC063, type is buried.
br7 = TFFE( _EQ015, GLOBAL( clk), VCC, VCC, _EQ016);
_EQ015 = a0 & !a1 & !a2 & !br7 & d7 & psr7 & !state~1 & !state~2
# a0 & !a1 & !a2 & br7 & !d7 & psr7 & !state~1 & !state~2;
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