📄 poc.rpt
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Project Information f:\poc\poc.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/10/2007 00:47:04
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
POC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
poc EPM7064AEUC49-4 16 18 0 28 4 43 %
User Pins: 16 18 0
Project Information f:\poc\poc.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information f:\poc\poc.rpt
** STATE MACHINE ASSIGNMENTS **
state: MACHINE
OF BITS (
state~2,
state~1
)
WITH STATES (
q0 = B"00",
q1 = B"10",
q2 = B"01"
);
Device-Specific Information: f:\poc\poc.rpt
poc
***** Logic for device 'poc' compiled without errors.
Device: EPM7064AEUC49-4
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: f:\poc\poc.rpt
poc
** ERROR SUMMARY **
Info: Chip 'poc' in device 'EPM7064AEUC49-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
-------------------------
| 1 2 3 4 5 6 7 |
|G o o o o o o o G|
|F o o o o o o o F|
|E o o o o o o o E|
|D o o o o o o o D|
|C o o o o o o o C|
|B o o o o o o o B|
|A o o o o o o o A|
| 1 2 3 4 5 6 7 |
-------------------------
EPM7064AEUC49-4
Bottom View
G d1 d6 d0 a1 psr3 psr5 psr1
F #TMS d7 d2 GND psr4 tr #TCK
E pd3 VCCIO d4 VCCINT psr2 GND pd2
D rw cs pd0 reset pd1 pd6 psr7
C rdy GND d3 psr0 pd7 VCCIO pd5
B #TDI a0 VCCINT GND GND pd4 #TDO
A d5 a2 GND GND clk nirq psr6
1 2 3 4 5 6 7
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\poc\poc.rpt
poc
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 9/ 9(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 2/16( 12%) 10/10(100%) 1/16( 6%) 10/36( 27%)
C: LC33 - LC48 10/16( 62%) 9/ 9(100%) 2/16( 12%) 25/36( 69%)
D: LC49 - LC64 16/16(100%) 9/ 9(100%) 5/16( 31%) 28/36( 77%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 37/37 (100%)
Total logic cells used: 28/64 ( 43%)
Total shareable expanders used: 4/64 ( 6%)
Total Turbo logic cells used: 28/64 ( 43%)
Total shareable expanders not available (n/a): 4/64 ( 6%)
Average fan-in: 9.75
Total fan-in: 273
Total input pins required: 16
Total fast input logic cells required: 0
Total output pins required: 18
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 28
Total flipflops required: 27
Total product terms required: 94
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 2
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: f:\poc\poc.rpt
poc
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
B2 (9) (A) INPUT 0 0 0 0 0 9 9 a0
G4 (17) (B) INPUT 0 0 0 0 0 9 9 a1
A2 (14) (A) INPUT 0 0 0 0 0 9 9 a2
A5 - - INPUT G 0 0 0 0 0 0 0 clk
D2 (1) (A) INPUT 0 0 0 0 0 17 10 cs
G3 (19) (B) INPUT 0 0 0 0 0 1 1 d0
G1 (22) (B) INPUT 0 0 0 0 0 1 1 d1
F3 (20) (B) INPUT 0 0 0 0 0 1 1 d2
C3 (16) (A) INPUT 0 0 0 0 0 1 1 d3
E3 (18) (B) INPUT 0 0 0 0 0 1 1 d4
A1 (11) (A) INPUT 0 0 0 0 0 1 1 d5
G2 (21) (B) INPUT 0 0 0 0 0 1 1 d6
F2 (24) (B) INPUT 0 0 0 0 0 1 1 d7
C1 (5) (A) INPUT 0 0 0 0 0 10 2 rdy
D4 (4) (A) INPUT 0 0 0 0 0 17 10 reset
D1 (3) (A) INPUT 0 0 0 0 0 9 2 rw
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\poc\poc.rpt
poc
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
A6 59 D OUTPUT t 0 0 0 0 2 0 0 nirq
D3 25 B FF + t 1 1 0 4 4 1 0 pd0
D5 41 C FF + t 1 1 0 4 4 1 0 pd1
E7 46 C FF + t 1 1 0 4 4 1 0 pd2
E1 30 B FF + t 1 1 0 4 4 1 0 pd3
B6 53 D FF + t 1 1 0 4 4 1 0 pd4
C7 52 D FF + t 1 1 0 4 4 1 0 pd5
D6 51 D FF + t 1 1 0 4 4 1 0 pd6
C5 62 D FF + t 1 1 0 4 4 1 0 pd7
C4 64 D FF + t 1 1 0 6 3 2 0 psr0 (:51)
G7 39 C FF + t 1 1 0 6 3 1 0 psr1 (:50)
E5 33 C FF + t 1 1 0 6 3 1 0 psr2 (:49)
G5 35 C FF + t 1 1 0 6 3 1 0 psr3 (:48)
F5 36 C FF + t 1 1 0 6 3 1 0 psr4 (:47)
G6 37 C FF + t 1 1 0 6 3 1 0 psr5 (:46)
A7 57 D FF + t 1 1 0 6 3 1 0 psr6 (:45)
D7 49 D FF + t 2 1 1 7 3 3 9 psr7 (:44)
F6 40 C FF + t 2 1 1 7 4 1 0 tr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
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