mbr.rpt

cpu的vhdl设计实现加法减法乘法运算

-- Node name is ':44' 
-- Equation name is '_LC6_B11', type is buried 
_LC6_B11 = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  _LC2_B11 & !read_ram
         #  d_ram11 &  read_ram;

-- Node name is ':46' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC6_C21 & !read_ram
         #  d_ram10 &  read_ram;

-- Node name is ':48' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC4_C21 & !read_ram
         #  d_ram9 &  read_ram;

-- Node name is ':50' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC2_C21 & !read_ram
         #  d_ram8 &  read_ram;

-- Node name is ':52' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC7_A15 & !read_ram
         #  d_ram7 &  read_ram;

-- Node name is ':54' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC6_A15 & !read_ram
         #  d_ram6 &  read_ram;

-- Node name is ':56' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  _LC4_A15 & !read_ram
         #  d_ram5 &  read_ram;

-- Node name is ':58' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC2_A15 & !read_ram
         #  d_ram4 &  read_ram;

-- Node name is ':60' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC7_B24 & !read_ram
         #  d_ram3 &  read_ram;

-- Node name is ':62' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC5_B24 & !read_ram
         #  d_ram2 &  read_ram;

-- Node name is ':64' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC4_B24 & !read_ram
         #  d_ram1 &  read_ram;

-- Node name is ':66' 
-- Equation name is '_LC6_B24', type is buried 
_LC6_B24 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  _LC3_B24 & !read_ram
         #  d_ram0 &  read_ram;

-- Node name is ':243' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = LCELL( _EQ017);
  _EQ017 =  d_acc15 &  ld_acc
         #  _LC3_C21 & !ld_acc;

-- Node name is ':255' 
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = LCELL( _EQ018);
  _EQ018 =  d_acc14 &  ld_acc
         #  _LC3_B11 & !ld_acc;

-- Node name is ':264' 
-- Equation name is '_LC5_B11', type is buried 
_LC5_B11 = LCELL( _EQ019);
  _EQ019 =  d_acc13 &  ld_acc
         #  _LC1_B11 & !ld_acc;

-- Node name is ':273' 
-- Equation name is '_LC4_B11', type is buried 
_LC4_B11 = LCELL( _EQ020);
  _EQ020 =  d_acc12 &  ld_acc
         #  _LC8_B11 & !ld_acc;

-- Node name is ':282' 
-- Equation name is '_LC2_B11', type is buried 
_LC2_B11 = LCELL( _EQ021);
  _EQ021 =  d_acc11 &  ld_acc
         #  _LC6_B11 & !ld_acc;

-- Node name is ':291' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = LCELL( _EQ022);
  _EQ022 =  d_acc10 &  ld_acc
         #  _LC5_C21 & !ld_acc;

-- Node name is ':300' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ023);
  _EQ023 =  d_acc9 &  ld_acc
         #  _LC1_C21 & !ld_acc;

-- Node name is ':309' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = LCELL( _EQ024);
  _EQ024 =  d_acc8 &  ld_acc
         #  _LC7_C21 & !ld_acc;

-- Node name is ':318' 
-- Equation name is '_LC7_A15', type is buried 
_LC7_A15 = LCELL( _EQ025);
  _EQ025 =  d_acc7 &  ld_acc
         #  _LC5_A15 & !ld_acc;

-- Node name is ':327' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ026);
  _EQ026 =  d_acc6 &  ld_acc
         #  _LC3_A15 & !ld_acc;

-- Node name is ':336' 
-- Equation name is '_LC4_A15', type is buried 
_LC4_A15 = LCELL( _EQ027);
  _EQ027 =  d_acc5 &  ld_acc
         #  _LC1_A15 & !ld_acc;

-- Node name is ':345' 
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = LCELL( _EQ028);
  _EQ028 =  d_acc4 &  ld_acc
         #  _LC8_A15 & !ld_acc;

-- Node name is ':354' 
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = LCELL( _EQ029);
  _EQ029 =  d_acc3 &  ld_acc
         #  _LC2_B24 & !ld_acc;

-- Node name is ':363' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = LCELL( _EQ030);
  _EQ030 =  d_acc2 &  ld_acc
         #  _LC8_B24 & !ld_acc;

-- Node name is ':372' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = LCELL( _EQ031);
  _EQ031 =  d_acc1 &  ld_acc
         #  _LC1_B24 & !ld_acc;

-- Node name is ':381' 
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ032);
  _EQ032 =  d_acc0 &  ld_acc
         #  _LC6_B24 & !ld_acc;



Project Information                                          e:\ldmcpu\mbr.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,695K