📄 car.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ldmcpu\car.rpt
car
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\ldmcpu\car.rpt
car
** EQUATIONS **
add1 : INPUT;
clk : INPUT;
d_branch0 : INPUT;
d_branch1 : INPUT;
d_branch2 : INPUT;
d_branch3 : INPUT;
d_branch4 : INPUT;
d_branch5 : INPUT;
d_branch6 : INPUT;
d_branch7 : INPUT;
load : INPUT;
reset : INPUT;
-- Node name is 'out_car0'
-- Equation name is 'out_car0', type is output
out_car0 = _LC1_A23;
-- Node name is 'out_car1'
-- Equation name is 'out_car1', type is output
out_car1 = _LC3_A23;
-- Node name is 'out_car2'
-- Equation name is 'out_car2', type is output
out_car2 = _LC2_A23;
-- Node name is 'out_car3'
-- Equation name is 'out_car3', type is output
out_car3 = _LC6_A21;
-- Node name is 'out_car4'
-- Equation name is 'out_car4', type is output
out_car4 = _LC5_A21;
-- Node name is 'out_car5'
-- Equation name is 'out_car5', type is output
out_car5 = _LC6_A15;
-- Node name is 'out_car6'
-- Equation name is 'out_car6', type is output
out_car6 = _LC4_A15;
-- Node name is 'out_car7'
-- Equation name is 'out_car7', type is output
out_car7 = _LC8_A23;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ001);
_EQ001 = _LC1_A23 & _LC3_A23;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ002);
_EQ002 = _LC1_A23 & _LC2_A23 & _LC3_A23;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ003);
_EQ003 = _LC1_A23 & _LC2_A23 & _LC3_A23 & _LC6_A21;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ004);
_EQ004 = _LC4_A21 & _LC5_A21;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = LCELL( _EQ005);
_EQ005 = _LC4_A21 & _LC5_A21 & _LC6_A15;
-- Node name is '|LPM_ADD_SUB:188|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = LCELL( _EQ006);
_EQ006 = _LC4_A15 & _LC4_A21 & _LC5_A21 & _LC6_A15;
-- Node name is ':13'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC8_A15 & !load
# d_branch7 & load;
-- Node name is ':15'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC5_A15 & !load
# d_branch6 & load;
-- Node name is ':17'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC2_A15 & !load
# d_branch5 & load;
-- Node name is ':19'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC3_A21 & !load
# d_branch4 & load;
-- Node name is ':21'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC2_A21 & !load
# d_branch3 & load;
-- Node name is ':23'
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC7_A23 & !load
# d_branch2 & load;
-- Node name is ':25'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC5_A23 & !load
# d_branch1 & load;
-- Node name is ':27'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC4_A23 & !load
# d_branch0 & load;
-- Node name is ':214'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = LCELL( _EQ015);
_EQ015 = add1 & !_LC7_A15 & _LC8_A23
# add1 & _LC7_A15 & !_LC8_A23
# !add1 & _LC8_A23 & !reset;
-- Node name is ':226'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = LCELL( _EQ016);
_EQ016 = add1 & !_LC3_A15 & _LC4_A15
# add1 & _LC3_A15 & !_LC4_A15
# !add1 & _LC4_A15 & !reset;
-- Node name is ':235'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ017);
_EQ017 = add1 & !_LC1_A15 & _LC6_A15
# add1 & _LC1_A15 & !_LC6_A15
# !add1 & _LC6_A15 & !reset;
-- Node name is ':244'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ018);
_EQ018 = add1 & !_LC4_A21 & _LC5_A21
# add1 & _LC4_A21 & !_LC5_A21
# !add1 & _LC5_A21 & !reset;
-- Node name is ':253'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ019);
_EQ019 = add1 & !_LC1_A21 & _LC6_A21
# add1 & _LC1_A21 & !_LC6_A21
# !add1 & _LC6_A21 & !reset;
-- Node name is ':262'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = LCELL( _EQ020);
_EQ020 = add1 & _LC2_A23 & !_LC6_A23
# add1 & !_LC2_A23 & _LC6_A23
# !add1 & _LC2_A23 & !reset;
-- Node name is ':271'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ021);
_EQ021 = add1 & !_LC1_A23 & _LC3_A23
# add1 & _LC1_A23 & !_LC3_A23
# !add1 & _LC3_A23 & !reset;
-- Node name is ':280'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ022);
_EQ022 = add1 & !_LC1_A23
# !add1 & _LC1_A23 & !reset;
Project Information e:\ldmcpu\car.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,431K
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