acc_alu.vhd

cpu的vhdl设计实现加法减法乘法运算

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity acc_alu is
port(br  :in std_logic_vector(15 downto 0);
     add,sub,logic_and,logic_or,logic_not,shiftr,shiftl,sr_in,sl_in,clk,reset  :in std_logic;
     acc_is0  :out std_logic;
     acc   :buffer std_logic_vector(15 downto 0));
end acc_alu;

architecture a of acc_alu is
begin 
  process(clk,reset)
    begin
      if clk'event and clk='1' then 
        if reset='1' then
          acc<="0000000000000000";
        end if;
        if add='1' then
           acc<=acc+br;
        end if;
        if sub='1' then
           acc<=acc-br;
        end if;
        if logic_and='1' then
           acc<=acc and br;
        end if;
        if logic_or='1' then
           acc<=acc or br;
        end if;
        if logic_not='1' then
           acc<=not br;
         end if;
         if shiftl='1' then
            acc<=acc(14 downto 0) & sl_in;
         end if;
         if shiftr='1' then
            acc<=sr_in & acc(15 downto 1);
         end if;
         end if;
         if acc="0000000000000000"  then
            acc_is0<='1';
          else  acc_is0<='0';
         end if;

  end process;
end a;