mar.vhd

cpu的vhdl设计实现加法减法乘法运算

library ieee;
use ieee.std_logic_1164.all;

entity mar is
port(d_pc,d_mb  :in std_logic_vector(7 downto 0);
     ld_pc,ld_mb,clk  :in std_logic;
     q    :out std_logic_vector(7 downto 0));
end mar;

architecture a of mar is
begin 
  process(clk)
    begin
      if clk'event and clk='1' then
        if ld_pc='1' then
          q<=d_pc;
         elsif ld_mb='1' then 
           q<=d_mb;
         end if;
       end if;
  end process;
end a;