mbr.vhd

cpu的vhdl设计实现加法减法乘法运算

library ieee;
use ieee.std_logic_1164.all;

entity mbr is
port(d_acc,d_ram  :in std_logic_vector(15 downto 0);
     ld_acc,read_ram,clk  :in std_logic;
     q    :out std_logic_vector(15 downto 0));
end mbr;

architecture a of mbr is
begin 
  process(clk)
    begin
      if clk'event and clk='1' then
        if read_ram='1' then
          q<=d_ram;
         elsif ld_acc='1' then 
           q<=d_acc;
         end if;
       end if;
  end process;
end a;