ir.vhd

cpu的vhdl设计实现加法减法乘法运算

library ieee;
use ieee.std_logic_1164.all;

entity ir is
port(d_mb  :in std_logic_vector(7 downto 0);
     ld_opcode,clk  :in std_logic;
     opcode :out std_logic_vector(7 downto 0));
end ir;

architecture a of ir is
begin 
  process(clk)
    begin
      if clk'event and clk='1' then
        if ld_opcode='1' then
          opcode<=d_mb;
        end if;
      end if;
  end process;
end a;