br.vhd

来自「cpu的vhdl设计实现加法减法乘法运算」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;

entity br is
port(d_mb  :in std_logic_vector(15 downto 0);
     ld_mb,clk  :in std_logic;
     br    :out std_logic_vector(15 downto 0));
end br;

architecture a of br is
begin 
  process(clk)
    begin
      if clk'event and clk='1' then
         if ld_mb='1' then 
            br<=d_mb;
         end if;
       end if;
  end process;
end a;