car.vhd

来自「cpu的vhdl设计实现加法减法乘法运算」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity car is
port(d_branch :in std_logic_vector(7 downto 0);
     load,add1,reset,clk  :in std_logic;
     out_car    :buffer std_logic_vector(7 downto 0));
end car;

architecture a of car is
begin 
  process(clk,reset)
    begin
      if clk'event and clk='1' then
        if reset='1' then
           out_car<="00000000";
        end if;
        if load='1' then
          out_car<=d_branch;
        elsif add1='1' then 
          out_car<=out_car+1;
        end if;
     end if;
  end process;
end a;