📄 cpu.rpt
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- 7 - F 05 DFFE + 0 3 0 4 |MBR:21|:44
- 4 - F 11 DFFE + 0 3 0 4 |MBR:21|:46
- 7 - F 04 DFFE + 0 3 0 4 |MBR:21|:48
- 3 - F 10 DFFE + 0 3 0 4 |MBR:21|:50
- 6 - A 08 DFFE + 0 3 0 5 |MBR:21|:52
- 6 - A 05 DFFE + 0 3 0 5 |MBR:21|:54
- 1 - A 09 DFFE + 0 3 0 5 |MBR:21|:56
- 8 - A 11 DFFE + 0 3 0 5 |MBR:21|:58
- 3 - A 10 DFFE + 0 3 0 5 |MBR:21|:60
- 2 - A 20 DFFE + 0 3 0 5 |MBR:21|:62
- 3 - A 03 DFFE + 0 3 0 5 |MBR:21|:64
- 1 - A 23 DFFE + 0 3 0 5 |MBR:21|:66
- 2 - F 06 OR2 0 3 0 1 |MBR:21|:243
- 1 - F 17 OR2 0 3 0 1 |MBR:21|:255
- 7 - F 16 OR2 0 3 0 1 |MBR:21|:264
- 2 - F 14 OR2 0 3 0 1 |MBR:21|:273
- 1 - F 05 OR2 0 3 0 1 |MBR:21|:282
- 3 - F 11 OR2 0 3 0 1 |MBR:21|:291
- 1 - F 04 OR2 0 3 0 1 |MBR:21|:300
- 6 - F 10 OR2 0 3 0 1 |MBR:21|:309
- 1 - A 08 OR2 0 3 0 1 |MBR:21|:318
- 2 - A 05 OR2 0 3 0 1 |MBR:21|:327
- 2 - A 09 OR2 0 3 0 1 |MBR:21|:336
- 1 - A 11 OR2 0 3 0 1 |MBR:21|:345
- 4 - A 10 OR2 0 3 0 1 |MBR:21|:354
- 3 - A 20 OR2 0 3 0 1 |MBR:21|:363
- 1 - A 03 OR2 0 3 0 1 |MBR:21|:372
- 5 - A 23 OR2 0 3 0 1 |MBR:21|:381
- 5 - A 20 AND2 0 2 0 1 |PC:42|LPM_ADD_SUB:188|addcore:adder|:121
- 6 - A 10 AND2 0 3 0 1 |PC:42|LPM_ADD_SUB:188|addcore:adder|:125
- 2 - A 10 AND2 0 4 0 2 |PC:42|LPM_ADD_SUB:188|addcore:adder|:129
- 4 - A 11 AND2 0 2 0 2 |PC:42|LPM_ADD_SUB:188|addcore:adder|:133
- 4 - A 09 AND2 0 2 0 2 |PC:42|LPM_ADD_SUB:188|addcore:adder|:137
- 1 - A 05 AND2 0 2 0 1 |PC:42|LPM_ADD_SUB:188|addcore:adder|:141
- 3 - A 08 DFFE + 0 3 0 2 |PC:42|:13
- 3 - A 05 DFFE + 0 3 0 3 |PC:42|:15
- 5 - A 09 DFFE + 0 3 0 3 |PC:42|:17
- 6 - A 11 DFFE + 0 3 0 3 |PC:42|:19
- 5 - A 10 DFFE + 0 3 0 3 |PC:42|:21
- 1 - A 20 DFFE + 0 3 0 4 |PC:42|:23
- 4 - A 03 DFFE + 0 3 0 5 |PC:42|:25
- 6 - A 23 DFFE + 0 3 0 6 |PC:42|:27
- 2 - A 08 OR2 0 4 0 1 |PC:42|:214
- 5 - A 05 OR2 0 4 0 1 |PC:42|:226
- 3 - A 09 OR2 0 4 0 1 |PC:42|:235
- 3 - A 11 OR2 0 4 0 1 |PC:42|:244
- 7 - A 10 OR2 0 4 0 1 |PC:42|:253
- 6 - A 20 OR2 0 4 0 1 |PC:42|:262
- 2 - A 03 OR2 0 4 0 1 |PC:42|:271
- 7 - A 23 OR2 0 3 0 1 |PC:42|:280
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 39/ 96( 40%) 36/ 48( 75%) 16/ 48( 33%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 10/ 96( 10%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 15/ 96( 15%) 19/ 48( 39%) 1/ 48( 2%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
D: 7/ 96( 7%) 8/ 48( 16%) 1/ 48( 2%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
E: 7/ 96( 7%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
F: 56/ 96( 58%) 37/ 48( 77%) 30/ 48( 62%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 14/24( 58%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 80 clk
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** EQUATIONS **
clk : INPUT;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _EC7_B;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _EC3_B;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _EC6_B;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _EC1_B;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _EC8_D;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _EC7_C;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _EC2_B;
-- Node name is 'c7'
-- Equation name is 'c7', type is output
c7 = _EC3_C;
-- Node name is 'c8'
-- Equation name is 'c8', type is output
c8 = _EC5_C;
-- Node name is 'c9'
-- Equation name is 'c9', type is output
c9 = _EC4_C;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _EC5_B;
-- Node name is 'c11'
-- Equation name is 'c11', type is output
c11 = _EC4_B;
-- Node name is 'c12'
-- Equation name is 'c12', type is output
c12 = _EC8_B;
-- Node name is 'c13'
-- Equation name is 'c13', type is output
c13 = _EC8_C;
-- Node name is 'c14'
-- Equation name is 'c14', type is output
c14 = _EC1_C;
-- Node name is 'c15'
-- Equation name is 'c15', type is output
c15 = _EC6_C;
-- Node name is 'c⌨️ 快捷键说明
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