📄 cpu.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - F -- OUTPUT 0 1 0 0 c0
32 - - F -- OUTPUT 0 1 0 0 c1
33 - - F -- OUTPUT 0 1 0 0 c2
79 - - F -- OUTPUT 0 1 0 0 c3
30 - - F -- OUTPUT 0 1 0 0 c4
7 - - A -- OUTPUT 0 1 0 0 c5
144 - - A -- OUTPUT 0 1 0 0 c6
100 - - A -- OUTPUT 0 1 0 0 c7
102 - - A -- OUTPUT 0 1 0 0 c8
12 - - C -- OUTPUT 0 1 0 0 c9
13 - - C -- OUTPUT 0 1 0 0 c10
101 - - A -- OUTPUT 0 1 0 0 c11
9 - - B -- OUTPUT 0 1 0 0 c12
92 - - C -- OUTPUT 0 1 0 0 c13
8 - - A -- OUTPUT 0 1 0 0 c14
97 - - B -- OUTPUT 0 1 0 0 c15
87 - - E -- OUTPUT 0 1 0 0 c16
91 - - C -- OUTPUT 0 1 0 0 c17
88 - - D -- OUTPUT 0 1 0 0 c18
90 - - C -- OUTPUT 0 1 0 0 c19
14 - - C -- OUTPUT 0 1 0 0 c20
27 - - E -- OUTPUT 0 1 0 0 c21
86 - - E -- OUTPUT 0 1 0 0 c22
29 - - E -- OUTPUT 0 1 0 0 c23
19 - - D -- OUTPUT 0 1 0 0 c24
78 - - F -- OUTPUT 0 1 0 0 c25
21 - - D -- OUTPUT 0 1 0 0 c26
18 - - D -- OUTPUT 0 1 0 0 c27
23 - - D -- OUTPUT 0 1 0 0 c28
22 - - D -- OUTPUT 0 1 0 0 c29
98 - - B -- OUTPUT 0 1 0 0 c30
20 - - D -- OUTPUT 0 1 0 0 c31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 16 OR2 0 4 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry1
- 4 - A 21 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry2
- 1 - A 02 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry3
- 8 - A 12 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry4
- 2 - C 04 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry5
- 1 - C 08 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry6
- 7 - C 05 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry7
- 4 - F 02 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry8
- 3 - F 19 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry9
- 2 - F 21 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry10
- 2 - F 23 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry11
- 1 - F 23 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry12
- 2 - F 16 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry13
- 4 - F 18 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|pcarry14
- 3 - A 16 OR2 0 4 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:178
- 3 - A 21 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:179
- 8 - A 02 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:180
- 3 - A 12 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:181
- 4 - C 04 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:182
- 3 - C 08 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:183
- 1 - C 05 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:184
- 2 - F 02 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:185
- 2 - F 19 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:186
- 1 - F 21 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:187
- 1 - F 22 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:188
- 3 - F 23 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:189
- 8 - F 16 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:190
- 1 - F 18 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:191
- 3 - F 24 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:440|addcore:adder|:192
- 5 - A 16 OR2 0 4 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry1
- 5 - A 21 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry2
- 4 - A 02 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry3
- 4 - A 12 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry4
- 8 - C 04 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry5
- 4 - C 08 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry6
- 4 - C 05 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry7
- 6 - F 02 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry8
- 8 - F 19 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry9
- 3 - F 21 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry10
- 8 - F 22 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry11
- 1 - F 15 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry12
- 4 - F 15 OR2 0 3 0 2 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry13
- 7 - F 18 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|pcarry14
- 6 - A 16 OR2 s 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|~178~1
- 2 - A 21 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:179
- 5 - A 02 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:180
- 1 - A 12 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:181
- 1 - C 04 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:182
- 6 - C 08 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:183
- 3 - C 05 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:184
- 5 - F 02 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:185
- 5 - F 19 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:186
- 5 - F 21 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:187
- 4 - F 22 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:188
- 6 - F 23 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:189
- 2 - F 15 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:190
- 3 - F 18 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:191
- 5 - F 24 OR2 0 3 0 1 |ACC_ALU:45|LPM_ADD_SUB:656|addcore:adder|:192
- 8 - F 17 DFFE + 0 3 0 9 |ACC_ALU:45|:29
- 4 - F 17 DFFE + 0 3 0 11 |ACC_ALU:45|:31
- 2 - F 08 DFFE + 0 3 0 11 |ACC_ALU:45|:33
- 6 - F 14 DFFE + 0 3 0 11 |ACC_ALU:45|:35
- 3 - F 13 DFFE + 0 3 0 11 |ACC_ALU:45|:37
- 2 - F 13 DFFE + 0 3 0 11 |ACC_ALU:45|:39
- 1 - F 13 DFFE + 0 3 0 11 |ACC_ALU:45|:41
- 2 - F 10 DFFE + 0 3 0 11 |ACC_ALU:45|:43
- 1 - F 10 DFFE + 0 3 0 11 |ACC_ALU:45|:45
- 1 - C 06 DFFE + 0 3 0 11 |ACC_ALU:45|:47
- 3 - A 07 DFFE + 0 3 0 11 |ACC_ALU:45|:49
- 1 - A 07 DFFE + 0 3 0 11 |ACC_ALU:45|:51
- 5 - A 07 DFFE + 0 3 0 11 |ACC_ALU:45|:53
- 2 - A 07 DFFE + 0 3 0 11 |ACC_ALU:45|:55
- 2 - A 18 DFFE + 0 3 0 11 |ACC_ALU:45|:57
- 4 - A 18 DFFE + 0 3 0 12 |ACC_ALU:45|:59
- 4 - F 24 OR2 0 4 0 1 |ACC_ALU:45|:482
- 2 - F 18 OR2 0 4 0 1 |ACC_ALU:45|:488
- 5 - F 16 OR2 0 4 0 1 |ACC_ALU:45|:494
- 4 - F 23 OR2 0 4 0 1 |ACC_ALU:45|:500
- 2 - F 22 OR2 0 4 0 1 |ACC_ALU:45|:506
- 4 - F 21 OR2 0 4 0 1 |ACC_ALU:45|:512
- 4 - F 19 OR2 0 4 0 1 |ACC_ALU:45|:518
- 3 - F 02 OR2 0 4 0 1 |ACC_ALU:45|:524
- 2 - C 05 OR2 0 4 0 1 |ACC_ALU:45|:530
- 5 - C 08 OR2 0 4 0 1 |ACC_ALU:45|:536
- 5 - C 04 OR2 0 4 0 1 |ACC_ALU:45|:542
- 5 - A 12 OR2 0 4 0 1 |ACC_ALU:45|:548
- 8 - A 10 OR2 0 4 0 1 |ACC_ALU:45|:554
- 6 - A 21 OR2 0 4 0 1 |ACC_ALU:45|:560
- 4 - A 16 OR2 0 4 0 1 |ACC_ALU:45|:566
- 4 - A 23 OR2 0 4 0 1 |ACC_ALU:45|:572
- 6 - F 24 OR2 0 3 0 1 |ACC_ALU:45|:698
- 5 - F 18 OR2 0 3 0 1 |ACC_ALU:45|:704
- 3 - F 15 OR2 0 3 0 1 |ACC_ALU:45|:710
- 7 - F 23 OR2 0 3 0 1 |ACC_ALU:45|:716
- 5 - F 22 OR2 0 3 0 1 |ACC_ALU:45|:722
- 7 - F 21 OR2 0 3 0 1 |ACC_ALU:45|:728
- 6 - F 19 OR2 0 3 0 1 |ACC_ALU:45|:734
- 7 - F 02 OR2 0 3 0 1 |ACC_ALU:45|:740
- 5 - C 05 OR2 0 3 0 1 |ACC_ALU:45|:746
- 7 - C 08 OR2 0 3 0 1 |ACC_ALU:45|:752
- 6 - C 04 OR2 0 3 0 1 |ACC_ALU:45|:758
- 6 - A 12 OR2 0 3 0 1 |ACC_ALU:45|:764
- 1 - A 10 OR2 0 3 0 1 |ACC_ALU:45|:770
- 7 - A 21 OR2 0 3 0 1 |ACC_ALU:45|:776
- 7 - A 16 OR2 0 4 0 1 |ACC_ALU:45|:782
- 1 - A 18 OR2 0 4 0 1 |ACC_ALU:45|:788
- 7 - F 24 OR2 0 4 0 1 |ACC_ALU:45|:929
- 8 - F 18 OR2 0 4 0 1 |ACC_ALU:45|:935
- 5 - F 15 OR2 0 4 0 1 |ACC_ALU:45|:941
- 8 - F 23 OR2 0 4 0 1 |ACC_ALU:45|:947
- 6 - F 22 OR2 0 4 0 1 |ACC_ALU:45|:953
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