📄 cpu.rpt
字号:
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S G G G G V S S S S S S S S S S S S S
E E E E G E E E E V E E E E G E N N N N C E E E E E E E V E E E E E E
R R R R N R R R R C R R R R N R D D D D C R R R R R R R C R R R R R R
V V V V D V V V V C V V V V D V I I I I I V V V V V V V C V V V V V V
c E E E E I E E E E I E E E E I E N N N N N E E E E E E E I E E E E E E
6 D D D D O D D D D O D D D D O D T T T T T D D D D D D D O D D D D D D
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/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
c5 | 7 102 | c8
c14 | 8 101 | c11
c12 | 9 100 | c7
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | c30
c9 | 12 97 | c15
c10 | 13 96 | RESERVED
c20 | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | c13
c27 | 18 91 | c17
c24 | 19 EPF10K20TC144-3 90 | c19
c31 | 20 89 | RESERVED
c26 | 21 88 | c18
c29 | 22 87 | c16
c28 | 23 86 | c22
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
c21 | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
c23 | 29 80 | c0
c4 | 30 79 | c3
RESERVED | 31 78 | c25
c1 | 32 77 | ^MSEL0
c2 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V G c G G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E N E C C N l N N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S D S C C D k D D D S S C S S S S D S S S S C S
E E E I E E E E I E E E E I E I I I I I I E E I E E E E I E E E E I E
R R R O R R R R O R R R R O R N N N N N N R R O R R R R O R R R R O R
V V V V V V V V V V V V T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 6/ 8( 75%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
A2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%)
A3 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A5 6/ 8( 75%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A7 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A8 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
A9 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
A10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 15/22( 68%)
A11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A12 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
A20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 14/22( 63%)
A21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A23 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
C4 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
C5 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C6 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
C9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
F1 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
F2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
F4 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
F5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 13/22( 59%)
F6 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
F7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 20/22( 90%)
F9 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
F10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
F11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
F12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
F14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
F15 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F16 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 12/22( 54%)
F17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
F18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
F24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 0/2 2/2 17/22( 77%)
B25 8/8 (100%) 11/8 (137%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
C25 8/8 (100%) 9/8 (112%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
D25 8/8 (100%) 3/8 ( 37%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
E25 8/8 (100%) 6/8 ( 75%) 7/8 ( 87%) 0/2 2/2 8/22( 36%)
F25 8/8 (100%) 1/8 ( 12%) 8/8 (100%) 0/2 2/2 17/22( 77%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 32/96 ( 33%)
Total logic cells used: 306/1152 ( 26%)
Total embedded cells used: 48/48 (100%)
Total EABs used: 6/6 (100%)
Average fan-in: 3.23/4 ( 80%)
Total fan-in: 989/4608 ( 21%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 306
Total flipflops required: 80
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 6 8 7 1 6 0 8 7 8 8 8 8 8 0 0 0 8 1 8 0 8 8 0 8 0 116/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
C: 0 0 0 8 8 3 0 8 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 28/8
D: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
E: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
F: 8 8 2 7 8 7 1 8 8 8 8 1 8 8 8 7 8 8 8 8 1 8 8 8 8 162/8
Total: 14 16 9 16 22 10 9 23 17 16 16 9 48 8 8 7 16 9 16 8 9 16 8 16 8 306/48
Device-Specific Information: e:\ldmcpu\cpu.rpt
cpu
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