branchlogic.vhd

cpu的vhdl设计实现加法减法乘法运算

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity BranchLogic is
port(d_rom :in std_logic_vector(2 downto 0);
     flags :in std_logic;
     opcode     :in std_logic_vector(7 downto 0);
     out_branch  : out std_logic_vector(7 downto 0);
     load,add1,reset  : out std_logic);
end BranchLogic;

architecture a of BranchLogic is
begin 
  process(d_rom,flags,opcode)
    begin
      if d_rom="100"  then
         reset<='1';
         add1<='0';
         load<='0';
      end if;
      if d_rom="010" then
         if opcode="01010000" and  flags='1' then
            out_branch<=opcode+1;
            add1<='0';
            load<='1';
            reset<='0';
         else   
            out_branch<=opcode;
            add1<='0';
            load<='1';
            reset<='0' ;         
       end if;
     end if;
     if d_rom="001" then
         add1<='1' ;
         reset<='0';
         load<='0';
     end if;
     if d_rom="000" then
         add1<='0';
         load<='0';    
         reset<='0';
     end if;
  end  process;
end a;