📄 branchlogic.rpt
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Device-Specific Information: e:\ldmcpu\branchlogic.rpt
branchlogic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ldmcpu\branchlogic.rpt
branchlogic
** EQUATIONS **
d_rom0 : INPUT;
d_rom1 : INPUT;
d_rom2 : INPUT;
flags : INPUT;
opcode0 : INPUT;
opcode1 : INPUT;
opcode2 : INPUT;
opcode3 : INPUT;
opcode4 : INPUT;
opcode5 : INPUT;
opcode6 : INPUT;
opcode7 : INPUT;
-- Node name is 'add1'
-- Equation name is 'add1', type is output
add1 = _LC7_C21;
-- Node name is 'load'
-- Equation name is 'load', type is output
load = _LC4_C21;
-- Node name is 'out_branch0'
-- Equation name is 'out_branch0', type is output
out_branch0 = _LC4_B23;
-- Node name is 'out_branch1'
-- Equation name is 'out_branch1', type is output
out_branch1 = _LC5_B23;
-- Node name is 'out_branch2'
-- Equation name is 'out_branch2', type is output
out_branch2 = _LC3_C21;
-- Node name is 'out_branch3'
-- Equation name is 'out_branch3', type is output
out_branch3 = _LC3_B23;
-- Node name is 'out_branch4'
-- Equation name is 'out_branch4', type is output
out_branch4 = _LC7_B23;
-- Node name is 'out_branch5'
-- Equation name is 'out_branch5', type is output
out_branch5 = _LC5_C21;
-- Node name is 'out_branch6'
-- Equation name is 'out_branch6', type is output
out_branch6 = _LC1_B23;
-- Node name is 'out_branch7'
-- Equation name is 'out_branch7', type is output
out_branch7 = _LC2_C21;
-- Node name is 'reset'
-- Equation name is 'reset', type is output
reset = _LC1_C21;
-- Node name is ':111'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ001);
_EQ001 = !d_rom0 & d_rom1 & !d_rom2;
-- Node name is '~145~1'
-- Equation name is '~145~1', location is LC2_B23, type is buried.
-- synthesized logic cell
_LC2_B23 = LCELL( _EQ002);
_EQ002 = opcode4 & !opcode5 & opcode6;
-- Node name is '~145~2'
-- Equation name is '~145~2', location is LC6_B23, type is buried.
-- synthesized logic cell
_LC6_B23 = LCELL( _EQ003);
_EQ003 = flags & !opcode1 & !opcode2;
-- Node name is ':145'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = LCELL( _EQ004);
_EQ004 = _LC2_B23 & _LC6_B23 & !opcode3 & !opcode7;
-- Node name is ':323'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ005);
_EQ005 = _LC2_C21 & !_LC8_C21
# _LC8_C21 & opcode7;
-- Node name is ':329'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ006);
_EQ006 = _LC1_B23 & !_LC8_C21
# _LC8_C21 & opcode6;
-- Node name is ':335'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = LCELL( _EQ007);
_EQ007 = _LC5_C21 & !_LC8_C21
# _LC8_C21 & opcode5;
-- Node name is ':341'
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = LCELL( _EQ008);
_EQ008 = _LC7_B23 & !_LC8_C21
# _LC8_C21 & opcode4;
-- Node name is ':347'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ009);
_EQ009 = _LC3_B23 & !_LC8_C21
# _LC8_C21 & opcode3;
-- Node name is ':353'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = LCELL( _EQ010);
_EQ010 = _LC3_C21 & !_LC8_C21
# _LC8_C21 & opcode2;
-- Node name is ':359'
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = LCELL( _EQ011);
_EQ011 = _LC5_B23 & !_LC8_C21
# _LC8_C21 & opcode1;
-- Node name is ':365'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ012);
_EQ012 = _LC4_B23 & !_LC8_C21
# _LC8_C21 & opcode0
# _LC8_B23 & _LC8_C21;
-- Node name is ':445'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ013);
_EQ013 = d_rom0 & !d_rom1 & !d_rom2
# d_rom0 & _LC7_C21
# d_rom1 & d_rom2 & _LC7_C21;
-- Node name is ':451'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ014);
_EQ014 = !d_rom0 & d_rom1 & !d_rom2
# d_rom1 & _LC4_C21
# d_rom0 & d_rom2 & _LC4_C21;
-- Node name is ':457'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ015);
_EQ015 = !d_rom0 & !d_rom1 & d_rom2
# d_rom2 & _LC1_C21
# d_rom0 & d_rom1 & _LC1_C21;
Project Information e:\ldmcpu\branchlogic.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,563K
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