📄 acc_alu.rpt
字号:
24 - - B -- OUTPUT 0 1 0 0 acc0
29 - - C -- OUTPUT 0 1 0 0 acc1
30 - - C -- OUTPUT 0 1 0 0 acc2
28 - - C -- OUTPUT 0 1 0 0 acc3
58 - - C -- OUTPUT 0 1 0 0 acc4
62 - - C -- OUTPUT 0 1 0 0 acc5
22 - - B -- OUTPUT 0 1 0 0 acc6
61 - - C -- OUTPUT 0 1 0 0 acc7
60 - - C -- OUTPUT 0 1 0 0 acc8
21 - - B -- OUTPUT 0 1 0 0 acc9
18 - - A -- OUTPUT 0 1 0 0 acc10
17 - - A -- OUTPUT 0 1 0 0 acc11
7 - - - 03 OUTPUT 0 1 0 0 acc12
19 - - A -- OUTPUT 0 1 0 0 acc13
8 - - - 03 OUTPUT 0 1 0 0 acc14
6 - - - 04 OUTPUT 0 1 0 0 acc15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\ldmcpu\acc_alu.rpt
acc_alu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 12 OR2 2 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry1
- 5 - C 12 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry2
- 2 - C 08 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry3
- 3 - C 05 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry4
- 4 - C 11 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry5
- 4 - C 03 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry6
- 1 - C 19 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry7
- 2 - C 20 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry8
- 1 - C 10 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry9
- 1 - B 02 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry10
- 1 - B 07 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry11
- 7 - B 07 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry12
- 4 - B 06 OR2 1 2 0 2 |LPM_ADD_SUB:440|addcore:adder|pcarry13
- 4 - B 05 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|pcarry14
- 1 - C 04 OR2 2 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:178
- 3 - C 12 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:179
- 1 - C 01 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:180
- 1 - C 05 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:181
- 2 - C 11 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:182
- 1 - C 03 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:183
- 2 - C 19 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:184
- 3 - C 20 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:185
- 3 - C 10 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:186
- 2 - B 02 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:187
- 1 - B 12 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:188
- 2 - B 07 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:189
- 7 - B 06 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:190
- 1 - B 05 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:191
- 1 - B 09 OR2 1 2 0 1 |LPM_ADD_SUB:440|addcore:adder|:192
- 5 - C 04 OR2 2 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry1
- 1 - C 08 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry2
- 5 - C 08 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry3
- 7 - C 05 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry4
- 8 - C 11 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry5
- 8 - C 03 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry6
- 4 - C 19 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry7
- 5 - C 20 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry8
- 2 - C 10 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry9
- 3 - B 02 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry10
- 2 - B 12 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry11
- 1 - B 06 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry12
- 3 - B 06 OR2 1 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry13
- 5 - B 05 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|pcarry14
- 4 - C 04 OR2 s 2 1 0 1 |LPM_ADD_SUB:656|addcore:adder|~178~1
- 6 - C 12 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:179
- 3 - C 08 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:180
- 5 - C 05 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:181
- 5 - C 11 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:182
- 5 - C 03 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:183
- 6 - C 19 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:184
- 6 - C 20 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:185
- 6 - C 10 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:186
- 6 - B 02 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:187
- 5 - B 12 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:188
- 4 - B 07 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:189
- 6 - B 06 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:190
- 3 - B 05 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:191
- 3 - B 09 OR2 1 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:192
- 8 - B 03 DFFE + 2 1 1 7 :29
- 1 - B 03 DFFE + 1 2 1 10 :31
- 7 - B 03 DFFE + 1 2 1 10 :33
- 6 - B 04 DFFE + 1 2 1 10 :35
- 2 - B 04 DFFE + 1 2 1 10 :37
- 8 - B 04 DFFE + 1 2 1 10 :39
- 1 - C 09 DFFE + 1 2 1 10 :41
- 4 - C 09 DFFE + 1 2 1 10 :43
- 3 - C 09 DFFE + 1 2 1 10 :45
- 2 - C 07 DFFE + 1 2 1 10 :47
- 1 - C 07 DFFE + 1 2 1 10 :49
- 7 - C 07 DFFE + 1 2 1 10 :51
- 2 - C 02 DFFE + 1 2 1 10 :53
- 7 - C 02 DFFE + 1 2 1 10 :55
- 8 - C 06 DFFE + 1 2 1 10 :57
- 6 - C 06 DFFE + 1 2 1 10 :59
- 2 - B 09 OR2 2 2 0 1 :482
- 2 - B 05 OR2 2 2 0 1 :488
- 6 - B 01 OR2 2 2 0 1 :494
- 3 - B 07 OR2 2 2 0 1 :500
- 3 - B 12 OR2 2 2 0 1 :506
- 4 - B 02 OR2 2 2 0 1 :512
- 5 - C 10 OR2 2 2 0 1 :518
- 4 - C 20 OR2 2 2 0 1 :524
- 3 - C 19 OR2 2 2 0 1 :530
- 3 - C 03 OR2 2 2 0 1 :536
- 3 - C 11 OR2 2 2 0 1 :542
- 2 - C 05 OR2 2 2 0 1 :548
- 8 - C 01 OR2 2 2 0 1 :554
- 4 - C 12 OR2 2 2 0 1 :560
- 2 - C 04 OR2 2 2 0 1 :566
- 1 - B 01 OR2 3 1 0 1 :572
- 5 - B 09 OR2 1 2 0 1 :698
- 6 - B 05 OR2 1 2 0 1 :704
- 4 - B 01 OR2 1 2 0 1 :710
- 5 - B 07 OR2 1 2 0 1 :716
- 6 - B 12 OR2 1 2 0 1 :722
- 7 - B 02 OR2 1 2 0 1 :728
- 7 - C 10 OR2 1 2 0 1 :734
- 7 - C 20 OR2 1 2 0 1 :740
- 7 - C 19 OR2 1 2 0 1 :746
- 6 - C 03 OR2 1 2 0 1 :752
- 6 - C 11 OR2 1 2 0 1 :758
- 6 - C 05 OR2 1 2 0 1 :764
- 4 - C 08 OR2 1 2 0 1 :770
- 7 - C 12 OR2 1 2 0 1 :776
- 6 - C 04 OR2 1 3 0 1 :782
- 2 - B 01 OR2 2 2 0 1 :788
- 6 - B 09 OR2 2 2 0 1 :929
- 8 - B 05 OR2 2 2 0 1 :935
- 5 - B 06 OR2 2 2 0 1 :941
- 6 - B 07 OR2 2 2 0 1 :947
- 7 - B 12 OR2 2 2 0 1 :953
- 8 - B 02 OR2 2 2 0 1 :959
- 8 - C 10 OR2 2 2 0 1 :965
- 8 - C 20 OR2 2 2 0 1 :971
- 8 - C 19 OR2 2 2 0 1 :977
- 7 - C 03 OR2 2 2 0 1 :983
- 7 - C 11 OR2 2 2 0 1 :989
- 8 - C 05 OR2 2 2 0 1 :995
- 7 - C 08 OR2 2 2 0 1 :1001
- 8 - C 12 OR2 2 2 0 1 :1007
- 7 - C 04 OR2 2 2 0 1 :1013
- 3 - B 01 OR2 2 2 0 1 :1019
- 7 - B 09 OR2 2 2 0 1 :1160
- 7 - B 05 OR2 2 2 0 1 :1166
- 8 - B 06 OR2 2 2 0 1 :1172
- 8 - B 07 OR2 2 2 0 1 :1178
- 8 - B 12 OR2 2 2 0 1 :1184
- 5 - B 02 OR2 2 2 0 1 :1190
- 4 - C 10 OR2 2 2 0 1 :1196
- 1 - C 20 OR2 2 2 0 1 :1202
- 5 - C 19 OR2 2 2 0 1 :1208
- 2 - C 03 OR2 2 2 0 1 :1214
- 1 - C 11 OR2 2 2 0 1 :1220
- 4 - C 05 OR2 2 2 0 1 :1226
- 8 - C 08 OR2 2 2 0 1 :1232
- 2 - C 12 OR2 2 2 0 1 :1238
- 8 - C 04 OR2 2 2 0 1 :1244
- 5 - B 01 OR2 2 2 0 1 :1250
- 4 - B 09 OR2 2 1 0 1 :1359
- 3 - B 03 OR2 2 1 0 1 :1365
- 2 - B 06 OR2 2 1 0 1 :1371
- 5 - B 04 OR2 2 1 0 1 :1377
- 4 - B 12 OR2 2 1 0 1 :1383
- 1 - B 04 OR2 2 1 0 1 :1389
- 7 - C 09 OR2 2 1 0 1 :1395
- 2 - C 16 OR2 2 1 0 1 :1401
- 2 - C 09 OR2 2 1 0 1 :1407
- 5 - C 07 OR2 2 1 0 1 :1413
- 3 - C 07 OR2 2 1 0 1 :1419
- 6 - C 02 OR2 2 1 0 1 :1425
- 6 - C 08 OR2 2 1 0 1 :1431
- 3 - C 02 OR2 2 1 0 1 :1437
- 3 - C 04 OR2 2 1 0 1 :1443
- 8 - B 01 OR2 2 1 0 1 :1449
- 5 - B 03 OR2 1 2 0 1 :1590
- 4 - B 03 OR2 1 2 0 1 :1596
- 2 - B 03 OR2 1 2 0 1 :1602
- 7 - B 04 OR2 1 2 0 1 :1608
- 4 - B 04 OR2 1 2 0 1 :1614
- 3 - B 04 OR2 1 2 0 1 :1620
- 8 - C 09 OR2 1 2 0 1 :1626
- 1 - C 16 OR2 1 2 0 1 :1632
- 6 - C 09 OR2 1 2 0 1 :1638
- 6 - C 07 OR2 1 2 0 1 :1644
- 4 - C 07 OR2 1 2 0 1 :1650
- 1 - C 02 OR2 1 2 0 1 :1656
- 5 - C 02 OR2 1 2 0 1 :1662
- 4 - C 02 OR2 1 2 0 1 :1668
- 3 - C 06 OR2 1 2 0 1 :1674
- 2 - C 06 OR2 2 1 0 1 :1680
- 4 - C 06 AND2 s 0 4 0 1 ~2048~1
- 5 - C 09 AND2 s 0 4 0 1 ~2048~2
- 8 - C 07 AND2 s 0 4 0 1 ~2048~3
- 5 - C 06 AND2 s 0 4 0 1 ~2048~4
- 1 - C 06 AND2 0 4 1 0 :2048
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\ldmcpu\acc_alu.rpt
acc_alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 10/ 96( 10%) 30/ 48( 62%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 25/ 96( 26%) 36/ 48( 75%) 4/ 48( 8%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\ldmcpu\acc_alu.rpt
acc_alu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: f:\ldmcpu\acc_alu.rpt
acc_alu
** EQUATIONS **
add : INPUT;
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