📄 ir.rpt
字号:
- 5 - C 11 DFFE + 2 0 1 0 :23
- 6 - C 11 DFFE + 2 0 1 0 :25
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\ldmcpu\ir.rpt
ir
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 7/ 96( 7%) 2/ 48( 4%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ldmcpu\ir.rpt
ir
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\ldmcpu\ir.rpt
ir
** EQUATIONS **
clk : INPUT;
d_mb0 : INPUT;
d_mb1 : INPUT;
d_mb2 : INPUT;
d_mb3 : INPUT;
d_mb4 : INPUT;
d_mb5 : INPUT;
d_mb6 : INPUT;
d_mb7 : INPUT;
ld_opcode : INPUT;
-- Node name is 'opcode0'
-- Equation name is 'opcode0', type is output
opcode0 = _LC6_C11;
-- Node name is 'opcode1'
-- Equation name is 'opcode1', type is output
opcode1 = _LC5_C11;
-- Node name is 'opcode2'
-- Equation name is 'opcode2', type is output
opcode2 = _LC1_C11;
-- Node name is 'opcode3'
-- Equation name is 'opcode3', type is output
opcode3 = _LC7_C11;
-- Node name is 'opcode4'
-- Equation name is 'opcode4', type is output
opcode4 = _LC3_C11;
-- Node name is 'opcode5'
-- Equation name is 'opcode5', type is output
opcode5 = _LC4_C11;
-- Node name is 'opcode6'
-- Equation name is 'opcode6', type is output
opcode6 = _LC2_C11;
-- Node name is 'opcode7'
-- Equation name is 'opcode7', type is output
opcode7 = _LC8_C11;
-- Node name is ':11'
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC8_C11 & !ld_opcode
# d_mb7 & ld_opcode;
-- Node name is ':13'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC2_C11 & !ld_opcode
# d_mb6 & ld_opcode;
-- Node name is ':15'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC4_C11 & !ld_opcode
# d_mb5 & ld_opcode;
-- Node name is ':17'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC3_C11 & !ld_opcode
# d_mb4 & ld_opcode;
-- Node name is ':19'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC7_C11 & !ld_opcode
# d_mb3 & ld_opcode;
-- Node name is ':21'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC1_C11 & !ld_opcode
# d_mb2 & ld_opcode;
-- Node name is ':23'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC5_C11 & !ld_opcode
# d_mb1 & ld_opcode;
-- Node name is ':25'
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC6_C11 & !ld_opcode
# d_mb0 & ld_opcode;
Project Information e:\ldmcpu\ir.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,847K
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