📄 sub.hif
字号:
HIF003
--
-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
branchlogic.vhd
{
branchlogic [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
{
19 [] [];
}
}
acc_alu.vhd
{
acc_alu [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
{
15 [] [];
}
}
car.vhd
{
car [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
{
14 [] [];
}
}
pc.vhd
{
pc [] [U1147235.DLS,U7449008.DLS,U2043679.DLS,U9092257.DLS,U5125632.DLS]
{
9 [] [];
}
}
mar.vhd
{
mar [] [U1147235.DLS,U7449008.DLS,U2043679.DLS]
{
8 [] [];
}
}
ir.vhd
{
ir [] [U1147235.DLS,U7449008.DLS,U2043679.DLS]
{
7 [] [];
}
}
br.vhd
{
br [] [U1147235.DLS,U7449008.DLS,U2043679.DLS]
{
6 [] [];
}
}
mbr.vhd
{
mbr [] [U1147235.DLS,U7449008.DLS,U2043679.DLS]
{
5 [] [];
}
}
lpm_ram_dq.tdf
{
lpm_ram_dq [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_WIDTHAD,LPM_NUMWORDS,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=REGISTERED,LPM_FILE=NO_FILE,DEVICE_FAMILY] [aglobal.inc,lpm_decode.inc,lpm_mux.inc,altram.inc]
{
3 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=16,LPM_WIDTHAD=8,LPM_INDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE=NO_FILE,DEVICE_FAMILY=FLEX10K] [data15,data14,data13,data12,data11,data10,data9,data8,data7,data6,data5,data4,data3,data2,data1,data0,address7,address6,address5,address4,address3,address2,address1,address0,we,q15,q14,q13,q12,q11,q10,q9,q8,q7,q6,q5,q4,q3,q2,q1,q0];
}
}
lpm_rom.tdf
{
lpm_rom [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_WIDTHAD,LPM_NUMWORDS,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=REGISTERED,LPM_FILE,DEVICE_FAMILY] [aglobal.inc,altrom.inc]
{
1 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=32,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_ADDRESS_CONTROL=UNREGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE=mul4_rom.mif,DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,q31,q30,q29,q28,q27,q26,q25,q24,q23,q22,q21,q20,q19,q18,q17,q16,q15,q14,q13,q12,q11,q10,q9,q8,q7,q6,q5,q4,q3,q2,q1,q0];
}
}
altrom.tdf
{
altrom [USE_LPM_FOR_AHDL_OPERATORS,WIDTH,AD_WIDTH,NUMWORDS,FILE,REGISTERINPUTMODE=DEFAULT,DEVICE_FAMILY] [aglobal.inc,lpm_mux.inc,lpm_decode.inc,memmodes.inc]
{
2 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=32,AD_WIDTH=8,NUMWORDS=256,FILE=mul4_rom.mif,REGISTERINPUTMODE=DEFAULT,DEVICE_FAMILY=FLEX10K] [Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21,Q22,Q23,Q24,Q25,Q26,Q27,Q28,Q29,Q30,Q31];
}
}
altram.tdf
{
altram [USE_LPM_FOR_AHDL_OPERATORS,WIDTH,AD_WIDTH,NUMWORDS,FILE=NO_FILE,REGISTERINPUTMODE=DEFAULT,USE_EAB=ON,DEVICE_FAMILY] [aglobal.inc,lpm_mux.inc,lpm_decode.inc,memmodes.inc]
{
4 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=16,AD_WIDTH=8,NUMWORDS=256,FILE=NO_FILE,REGISTERINPUTMODE=DEFAULT,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,Data8,Data9,Data10,Data11,Data12,Data13,Data14,Data15,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15];
}
}
lpm_add_sub.tdf
{
lpm_add_sub [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY,STYLE] [aglobal.inc,altshift.inc,bypassff.inc,look_add.inc,addcore.inc,lpm_add_sub.inc]
{
10 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=YES,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAA4,DATAA5,DATAA6,DATAA7,DATAB0,DATAB1,DATAB2,DATAB3,DATAB4,DATAB5,DATAB6,DATAB7,CIN,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4,RESULT5,RESULT6,RESULT7];
16 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=16,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA0,DATAA1,DATAA2,DATAA3,DATAA4,DATAA5,DATAA6,DATAA7,DATAA8,DATAA9,DATAA10,DATAA11,DATAA12,DATAA13,DATAA14,DATAA15,DATAB0,DATAB1,DATAB2,DATAB3,DATAB4,DATAB5,DATAB6,DATAB7,DATAB8,DATAB9,DATAB10,DATAB11,DATAB12,DATAB13,DATAB14,DATAB15,CIN,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4,RESULT5,RESULT6,RESULT7,RESULT8,RESULT9,RESULT10,RESULT11,RESULT12,RESULT13,RESULT14,RESULT15];
}
}
addcore.tdf
{
addcore [USE_LPM_FOR_AHDL_OPERATORS,width,CONSTANT_CIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH,DEVICE_FAMILY] [aglobal.inc,addcore.inc]
{
11 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=8,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,result0,result1,result2,result3,result4,result5,result6,result7];
17 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=16,CONSTANT_CIN=0,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,datab8,datab9,datab10,datab11,datab12,datab13,datab14,datab15,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,dataa8,dataa9,dataa10,dataa11,dataa12,dataa13,dataa14,dataa15,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10,result11,result12,result13,result14,result15];
}
}
altshift.tdf
{
altshift [USE_LPM_FOR_AHDL_OPERATORS,WIDTH=4,DEPTH=0] []
{
12 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,DEPTH=0] [data0,data1,data2,data3,data4,data5,data6,data7,result0,result1,result2,result3,result4,result5,result6,result7];
13 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=1,DEPTH=0] [data0,result0];
18 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=16,DEPTH=0] [data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,data11,data12,data13,data14,data15,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10,result11,result12,result13,result14,result15];
}
}
sub.gdf
{
sub [] []
{
0 [] [];
}
}
}
TREE
{
sub::(0,0):(0): sub.gdf
{
branchlogic::(0,0):(47): branchlogic.vhd
{
lpm_add_sub:10:(23,10):(170): lpm_add_sub.tdf
{
altshift:13:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
altshift:13:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
altshift:12:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
addcore:11:(212,4):(58,adder): addcore.tdf;
}
}
acc_alu::(0,0):(45): acc_alu.vhd
{
lpm_add_sub:16:(23,9):(656): lpm_add_sub.tdf
{
altshift:13:(226,2):(183,oflow_ext_latency_ffs): altshift.tdf;
altshift:13:(224,2):(175,carry_ext_latency_ffs): altshift.tdf;
altshift:18:(222,2):(137,result_ext_latency_ffs): altshift.tdf;
addcore:17:(212,4):(82,adder): addcore.tdf;
}
lpm_add_sub:16:(20,9):(440): lpm_add_sub.tdf
{
altshift:13:(226,2):(183,oflow_ext_latency_ffs): altshift.tdf;
altshift:13:(224,2):(175,carry_ext_latency_ffs): altshift.tdf;
altshift:18:(222,2):(137,result_ext_latency_ffs): altshift.tdf;
addcore:17:(212,4):(82,adder): addcore.tdf;
}
}
car::(0,0):(43): car.vhd
{
lpm_add_sub:10:(21,9):(188): lpm_add_sub.tdf
{
altshift:13:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
altshift:13:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
altshift:12:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
addcore:11:(212,4):(58,adder): addcore.tdf;
}
}
pc::(0,0):(42): pc.vhd
{
lpm_add_sub:10:(21,9):(188): lpm_add_sub.tdf
{
altshift:13:(226,2):(119,oflow_ext_latency_ffs): altshift.tdf;
altshift:13:(224,2):(111,carry_ext_latency_ffs): altshift.tdf;
altshift:12:(222,2):(89,result_ext_latency_ffs): altshift.tdf;
addcore:11:(212,4):(58,adder): addcore.tdf;
}
}
mar::(0,0):(30): mar.vhd;
ir::(0,0):(26): ir.vhd;
br::(0,0):(22): br.vhd;
mbr::(0,0):(21): mbr.vhd;
lpm_ram_dq::(0,0):(6): lpm_ram_dq.tdf
{
altram:4:(86,5):(70,sram): altram.tdf;
}
lpm_rom::(0,0):(3): lpm_rom.tdf
{
altrom:2:(63,3):(70,srom): altrom.tdf;
}
}
}
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