📄 cpu_add1_to_10.rpt
字号:
F8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 20/22( 90%)
F9 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
F10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
F11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
F12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
F14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
F15 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F16 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 12/22( 54%)
F17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
F18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F21 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
F24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 0/2 2/2 17/22( 77%)
B25 8/8 (100%) 11/8 (137%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
C25 8/8 (100%) 9/8 (112%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
D25 8/8 (100%) 3/8 ( 37%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
E25 8/8 (100%) 6/8 ( 75%) 7/8 ( 87%) 0/2 2/2 8/22( 36%)
F25 8/8 (100%) 1/8 ( 12%) 8/8 (100%) 0/2 2/2 17/22( 77%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 32/96 ( 33%)
Total logic cells used: 306/1152 ( 26%)
Total embedded cells used: 48/48 (100%)
Total EABs used: 6/6 (100%)
Average fan-in: 3.23/4 ( 80%)
Total fan-in: 989/4608 ( 21%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 306
Total flipflops required: 80
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 6 8 7 1 6 0 8 7 8 8 8 8 8 0 0 0 8 1 8 0 8 8 0 8 0 116/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
C: 0 0 0 8 8 3 0 8 1 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 28/8
D: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
E: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
F: 8 8 2 7 8 7 1 8 8 8 8 1 8 8 8 7 8 8 8 8 1 8 8 8 8 162/8
Total: 14 16 9 16 22 10 9 23 17 16 16 9 48 8 8 7 16 9 16 8 9 16 8 16 8 306/48
Device-Specific Information: e:\ldmcpu\cpu_add1_to_10.rpt
cpu_add1_to_10
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\ldmcpu\cpu_add1_to_10.rpt
cpu_add1_to_10
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - F -- OUTPUT 0 1 0 0 c0
32 - - F -- OUTPUT 0 1 0 0 c1
33 - - F -- OUTPUT 0 1 0 0 c2
79 - - F -- OUTPUT 0 1 0 0 c3
30 - - F -- OUTPUT 0 1 0 0 c4
7 - - A -- OUTPUT 0 1 0 0 c5
144 - - A -- OUTPUT 0 1 0 0 c6
100 - - A -- OUTPUT 0 1 0 0 c7
102 - - A -- OUTPUT 0 1 0 0 c8
12 - - C -- OUTPUT 0 1 0 0 c9
13 - - C -- OUTPUT 0 1 0 0 c10
101 - - A -- OUTPUT 0 1 0 0 c11
9 - - B -- OUTPUT 0 1 0 0 c12
92 - - C -- OUTPUT 0 1 0 0 c13
8 - - A -- OUTPUT 0 1 0 0 c14
97 - - B -- OUTPUT 0 1 0 0 c15
87 - - E -- OUTPUT 0 1 0 0 c16
91 - - C -- OUTPUT 0 1 0 0 c17
88 - - D -- OUTPUT 0 1 0 0 c18
90 - - C -- OUTPUT 0 1 0 0 c19
14 - - C -- OUTPUT 0 1 0 0 c20
27 - - E -- OUTPUT 0 1 0 0 c21
86 - - E -- OUTPUT 0 1 0 0 c22
29 - - E -- OUTPUT 0 1 0 0 c23
19 - - D -- OUTPUT 0 1 0 0 c24
78 - - F -- OUTPUT 0 1 0 0 c25
21 - - D -- OUTPUT 0 1 0 0 c26
18 - - D -- OUTPUT 0 1 0 0 c27
23 - - D -- OUTPUT 0 1 0 0 c28
22 - - D -- OUTPUT 0 1 0 0 c29
98 - - B -- OUTPUT 0 1 0 0 c30
20 - - D -- OUTPUT 0 1 0 0 c31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\ldmcpu\cpu_add1_to_10.rpt
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