📄 mar.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 7/ 96( 7%) 0/ 48( 0%) 2/ 48( 4%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ldmcpu\mar.rpt
mar
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\ldmcpu\mar.rpt
mar
** EQUATIONS **
clk : INPUT;
d_mb0 : INPUT;
d_mb1 : INPUT;
d_mb2 : INPUT;
d_mb3 : INPUT;
d_mb4 : INPUT;
d_mb5 : INPUT;
d_mb6 : INPUT;
d_mb7 : INPUT;
d_pc0 : INPUT;
d_pc1 : INPUT;
d_pc2 : INPUT;
d_pc3 : INPUT;
d_pc4 : INPUT;
d_pc5 : INPUT;
d_pc6 : INPUT;
d_pc7 : INPUT;
ld_mb : INPUT;
ld_pc : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC7_B18;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC2_B18;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC5_B18;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC1_B18;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC1_A13;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC3_A13;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC5_A13;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC4_A13;
-- Node name is ':20'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC8_A13 & !ld_pc
# d_pc7 & ld_pc;
-- Node name is ':22'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC7_A13 & !ld_pc
# d_pc6 & ld_pc;
-- Node name is ':24'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC6_A13 & !ld_pc
# d_pc5 & ld_pc;
-- Node name is ':26'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC2_A13 & !ld_pc
# d_pc4 & ld_pc;
-- Node name is ':28'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC8_B18 & !ld_pc
# d_pc3 & ld_pc;
-- Node name is ':30'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC6_B18 & !ld_pc
# d_pc2 & ld_pc;
-- Node name is ':32'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC4_B18 & !ld_pc
# d_pc1 & ld_pc;
-- Node name is ':34'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC3_B18 & !ld_pc
# d_pc0 & ld_pc;
-- Node name is ':131'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ009);
_EQ009 = _LC4_A13 & !ld_mb
# d_mb7 & ld_mb;
-- Node name is ':143'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ010);
_EQ010 = _LC5_A13 & !ld_mb
# d_mb6 & ld_mb;
-- Node name is ':152'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ011);
_EQ011 = _LC3_A13 & !ld_mb
# d_mb5 & ld_mb;
-- Node name is ':161'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ012);
_EQ012 = _LC1_A13 & !ld_mb
# d_mb4 & ld_mb;
-- Node name is ':170'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ013);
_EQ013 = _LC1_B18 & !ld_mb
# d_mb3 & ld_mb;
-- Node name is ':179'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ014);
_EQ014 = _LC5_B18 & !ld_mb
# d_mb2 & ld_mb;
-- Node name is ':188'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ015);
_EQ015 = _LC2_B18 & !ld_mb
# d_mb1 & ld_mb;
-- Node name is ':197'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = LCELL( _EQ016);
_EQ016 = _LC7_B18 & !ld_mb
# d_mb0 & ld_mb;
Project Information e:\ldmcpu\mar.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,343K
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