run_watch.vhd

来自「提供一个数字秒表的EDA设计实例」· VHDL 代码 · 共 96 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity run_watch is
  port(start,reset,clk: in std_logic;
       mic_0,mic_1,sec_0,sec_1,min_0,min_1: out std_logic_vector(3 downto 0));
end run_watch;

architecture behav of run_watch is 
  signal mic,sec: std_logic;
  signal mic_m_0,mic_m_1,sec_m_0,sec_m_1,min_m_0,min_m_1: std_logic_vector(3 downto 0); --中间信号
begin
  micp:process(reset,start,clk)
  begin
    if reset='1' then
       mic <= '0'; mic_m_0 <= (others=>'0'); mic_m_1 <= (others=>'0');
    elsif clk'event and clk='1' then
       if start='1' then
          if mic_m_0=9 then
             mic_m_0 <= (others=>'0');
             if mic_m_1=5 then
                mic_m_1 <= (others=>'0'); mic <= '1';
             else
                mic_m_1 <= mic_m_1 + 1; mic <= '0';
             end if;
          else
             mic_m_0 <= mic_m_0 + 1;
          end if;
       end if;
    end if;
  end process micp;
  secm:process(reset,start,mic)
  begin
    if reset='1' then
       sec_m_0 <= (others=>'0'); sec_m_1 <= (others=>'0');
    elsif mic'event and mic='1' then
       if start='1' then
          if sec_m_0=9 then
             sec_m_0 <= (others=>'0');
             if sec_m_1=5 then
                sec_m_1 <= (others=>'0'); sec <= '1';
             else
                sec_m_1 <= sec_m_1 + 1; sec <= '0';
             end if;
          else
             sec_m_0 <= sec_m_0 + 1;
          end if;
       end if;
    end if;
  end process secm;
  minm:process(reset,start,sec)
  begin
    if reset='1' then
       min_m_0 <= (others=>'0'); min_m_1 <= (others=>'0'); 
    elsif sec'event and sec='1' then
       if start='1' then
          if min_m_0=9 then
             min_m_0 <= (others=>'0');
             if min_m_1=5 then
                min_m_1 <= (others=>'0');
             else
                min_m_1 <= min_m_1 + 1;
             end if;
          else
             min_m_0 <= min_m_0 + 1;
          end if;
       end if;
    end if;
  end process minm;
  mic_0 <= mic_m_0; mic_1 <= mic_m_1; 
  sec_0 <= sec_m_0; sec_1 <= sec_m_1;
  min_0 <= min_m_0; min_1 <= min_m_1;
end behav;