📄 run_watch.rpt
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Logic cells placed in LAB 'B'
+------------------------------- LC25 mic_01
| +----------------------------- LC26 mic_02
| | +--------------------------- LC30 mic_03
| | | +------------------------- LC32 mic_10
| | | | +----------------------- LC23 mic_11
| | | | | +--------------------- LC21 mic_12
| | | | | | +------------------- LC17 mic_13
| | | | | | | +----------------- LC19 sec_01
| | | | | | | | +--------------- LC18 sec_02
| | | | | | | | | +------------- LC20 sec_03
| | | | | | | | | | +----------- LC24 sec_10
| | | | | | | | | | | +--------- LC22 sec_11
| | | | | | | | | | | | +------- LC31 sec_12
| | | | | | | | | | | | | +----- LC29 sec_13
| | | | | | | | | | | | | | +--- LC27 mic
| | | | | | | | | | | | | | | +- LC28 sec
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> * * * * * * * - - - - - - - * - | - * | <-- mic_01
LC26 -> * * * * * * * - - - - - - - * - | - * | <-- mic_02
LC30 -> * - * * * * * - - - - - - - * - | - * | <-- mic_03
LC32 -> - - - * * * * - - - - - - - * - | - * | <-- mic_10
LC23 -> - - - - * * * - - - - - - - * - | - * | <-- mic_11
LC21 -> - - - - * * * - - - - - - - * - | - * | <-- mic_12
LC17 -> - - - - * * * - - - - - - - * - | - * | <-- mic_13
LC19 -> - - - - - - - * * * * * * * - * | - * | <-- sec_01
LC18 -> - - - - - - - * * * * * * * - * | - * | <-- sec_02
LC20 -> - - - - - - - * - * * * * * - * | - * | <-- sec_03
LC24 -> - - - - - - - - - - * * * * - * | - * | <-- sec_10
LC22 -> - - - - - - - - - - - * * * - * | - * | <-- sec_11
LC31 -> - - - - - - - - - - - * * * - * | - * | <-- sec_12
LC29 -> - - - - - - - - - - - * * * - * | - * | <-- sec_13
LC27 -> - - - - - - - * * * * * * * * * | * * | <-- mic
LC28 -> - - - - - - - - - - - - - - - * | * * | <-- sec
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
5 -> * * * * * * * * * * * * * * * * | * * | <-- reset
4 -> * * * * * * * * * * * * * * * * | * * | <-- start
LC11 -> * * * * * * * - - - - - - - * - | - * | <-- mic_00
LC5 -> - - - - - - - * * * * * * * - * | - * | <-- sec_00
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is ':28' = 'mic'
-- Equation name is 'mic', location is LC027, type is buried.
mic = TFFE( _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = !mic & mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & !mic_11 &
mic_12 & !mic_13 & start
# mic & mic_00 & !mic_01 & !mic_02 & mic_03 & start & _X001;
_X001 = EXP( mic_10 & !mic_11 & mic_12 & !mic_13);
-- Node name is 'mic_00' = 'mic_m_00'
-- Equation name is 'mic_00', location is LC011, type is output.
mic_00 = TFFE( start, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is 'mic_01' = 'mic_m_01'
-- Equation name is 'mic_01', location is LC025, type is output.
mic_01 = TFFE( _EQ002, GLOBAL( clk), !reset, VCC, VCC);
_EQ002 = mic_00 & !mic_01 & mic_02 & start
# mic_00 & !mic_01 & !mic_03 & start
# mic_00 & mic_01 & start;
-- Node name is 'mic_02' = 'mic_m_02'
-- Equation name is 'mic_02', location is LC026, type is output.
mic_02 = TFFE( _EQ003, GLOBAL( clk), !reset, VCC, VCC);
_EQ003 = mic_00 & mic_01 & start;
-- Node name is 'mic_03' = 'mic_m_03'
-- Equation name is 'mic_03', location is LC030, type is output.
mic_03 = TFFE( _EQ004, GLOBAL( clk), !reset, VCC, VCC);
_EQ004 = mic_00 & !mic_01 & !mic_02 & mic_03 & start
# mic_00 & mic_01 & mic_02 & start;
-- Node name is 'mic_10' = 'mic_m_10'
-- Equation name is 'mic_10', location is LC032, type is output.
mic_10 = TFFE( _EQ005, GLOBAL( clk), !reset, VCC, VCC);
_EQ005 = mic_00 & !mic_01 & !mic_02 & mic_03 & start;
-- Node name is 'mic_11' = 'mic_m_11'
-- Equation name is 'mic_11', location is LC023, type is output.
mic_11 = TFFE( _EQ006, GLOBAL( clk), !reset, VCC, VCC);
_EQ006 = mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & !mic_11 &
mic_13 & start
# mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & !mic_11 &
!mic_12 & start
# mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & mic_11 & start;
-- Node name is 'mic_12' = 'mic_m_12'
-- Equation name is 'mic_12', location is LC021, type is output.
mic_12 = TFFE( _EQ007, GLOBAL( clk), !reset, VCC, VCC);
_EQ007 = mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & !mic_11 &
mic_12 & !mic_13 & start
# mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & mic_11 & start;
-- Node name is 'mic_13' = 'mic_m_13'
-- Equation name is 'mic_13', location is LC017, type is output.
mic_13 = TFFE( _EQ008, GLOBAL( clk), !reset, VCC, VCC);
_EQ008 = mic_00 & !mic_01 & !mic_02 & mic_03 & mic_10 & mic_11 &
mic_12 & start;
-- Node name is 'min_00' = 'min_m_00'
-- Equation name is 'min_00', location is LC003, type is output.
min_00 = TFFE( start, sec, !reset, VCC, VCC);
-- Node name is 'min_01' = 'min_m_01'
-- Equation name is 'min_01', location is LC004, type is output.
min_01 = TFFE( _EQ009, sec, !reset, VCC, VCC);
_EQ009 = min_00 & !min_01 & min_02 & start
# min_00 & !min_01 & !min_03 & start
# min_00 & min_01 & start;
-- Node name is 'min_02' = 'min_m_02'
-- Equation name is 'min_02', location is LC006, type is output.
min_02 = TFFE( _EQ010, sec, !reset, VCC, VCC);
_EQ010 = min_00 & min_01 & start;
-- Node name is 'min_03' = 'min_m_03'
-- Equation name is 'min_03', location is LC007, type is output.
min_03 = TFFE( _EQ011, sec, !reset, VCC, VCC);
_EQ011 = min_00 & !min_01 & !min_02 & min_03 & start
# min_00 & min_01 & min_02 & start;
-- Node name is 'min_10' = 'min_m_10'
-- Equation name is 'min_10', location is LC010, type is output.
min_10 = TFFE( _EQ012, sec, !reset, VCC, VCC);
_EQ012 = min_00 & !min_01 & !min_02 & min_03 & start;
-- Node name is 'min_11' = 'min_m_11'
-- Equation name is 'min_11', location is LC016, type is output.
min_11 = TFFE( _EQ013, sec, !reset, VCC, VCC);
_EQ013 = min_00 & !min_01 & !min_02 & min_03 & min_10 & !min_11 &
min_13 & start
# min_00 & !min_01 & !min_02 & min_03 & min_10 & !min_11 &
!min_12 & start
# min_00 & !min_01 & !min_02 & min_03 & min_10 & min_11 & start;
-- Node name is 'min_12' = 'min_m_12'
-- Equation name is 'min_12', location is LC012, type is output.
min_12 = TFFE( _EQ014, sec, !reset, VCC, VCC);
_EQ014 = min_00 & !min_01 & !min_02 & min_03 & min_10 & !min_11 &
min_12 & !min_13 & start
# min_00 & !min_01 & !min_02 & min_03 & min_10 & min_11 & start;
-- Node name is 'min_13' = 'min_m_13'
-- Equation name is 'min_13', location is LC008, type is output.
min_13 = TFFE( _EQ015, sec, !reset, VCC, VCC);
_EQ015 = min_00 & !min_01 & !min_02 & min_03 & min_10 & min_11 &
min_12 & !min_13 & start & _X002
# min_00 & !min_01 & !min_02 & min_03 & min_10 & min_11 &
min_12 & min_13 & start;
_X002 = EXP( min_10 & !min_11 & min_12);
-- Node name is ':45' = 'sec'
-- Equation name is 'sec', location is LC028, type is buried.
sec = TFFE( _EQ016, mic, VCC, VCC, VCC);
_EQ016 = !reset & !sec & sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 &
!sec_11 & sec_12 & !sec_13 & start
# !reset & sec & sec_00 & !sec_01 & !sec_02 & sec_03 & start &
_X003;
_X003 = EXP( sec_10 & !sec_11 & sec_12 & !sec_13);
-- Node name is 'sec_00' = 'sec_m_00'
-- Equation name is 'sec_00', location is LC005, type is output.
sec_00 = TFFE( start, mic, !reset, VCC, VCC);
-- Node name is 'sec_01' = 'sec_m_01'
-- Equation name is 'sec_01', location is LC019, type is output.
sec_01 = TFFE( _EQ017, mic, !reset, VCC, VCC);
_EQ017 = sec_00 & !sec_01 & sec_02 & start
# sec_00 & !sec_01 & !sec_03 & start
# sec_00 & sec_01 & start;
-- Node name is 'sec_02' = 'sec_m_02'
-- Equation name is 'sec_02', location is LC018, type is output.
sec_02 = TFFE( _EQ018, mic, !reset, VCC, VCC);
_EQ018 = sec_00 & sec_01 & start;
-- Node name is 'sec_03' = 'sec_m_03'
-- Equation name is 'sec_03', location is LC020, type is output.
sec_03 = TFFE( _EQ019, mic, !reset, VCC, VCC);
_EQ019 = sec_00 & !sec_01 & !sec_02 & sec_03 & start
# sec_00 & sec_01 & sec_02 & start;
-- Node name is 'sec_10' = 'sec_m_10'
-- Equation name is 'sec_10', location is LC024, type is output.
sec_10 = TFFE( _EQ020, mic, !reset, VCC, VCC);
_EQ020 = sec_00 & !sec_01 & !sec_02 & sec_03 & start;
-- Node name is 'sec_11' = 'sec_m_11'
-- Equation name is 'sec_11', location is LC022, type is output.
sec_11 = TFFE( _EQ021, mic, !reset, VCC, VCC);
_EQ021 = sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & !sec_11 &
sec_13 & start
# sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & !sec_11 &
!sec_12 & start
# sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & sec_11 & start;
-- Node name is 'sec_12' = 'sec_m_12'
-- Equation name is 'sec_12', location is LC031, type is output.
sec_12 = TFFE( _EQ022, mic, !reset, VCC, VCC);
_EQ022 = sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & !sec_11 &
sec_12 & !sec_13 & start
# sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & sec_11 & start;
-- Node name is 'sec_13' = 'sec_m_13'
-- Equation name is 'sec_13', location is LC029, type is output.
sec_13 = TFFE( _EQ023, mic, !reset, VCC, VCC);
_EQ023 = sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & sec_11 &
sec_12 & !sec_13 & start & _X004
# sec_00 & !sec_01 & !sec_02 & sec_03 & sec_10 & sec_11 &
sec_12 & sec_13 & start;
_X004 = EXP( sec_10 & !sec_11 & sec_12);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\run_watch\run_watch.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,315K
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