📄 run_watch.rpt
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Project Information d:\vhdl\run_watch\run_watch.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/11/2008 16:15:30
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
RUN_WATCH
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
run_watch
EPM7032LC44-6 3 24 0 26 4 81 %
User Pins: 3 24 0
Project Information d:\vhdl\run_watch\run_watch.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\vhdl\run_watch\run_watch.rpt
** FILE HIERARCHY **
|lpm_add_sub:159|
|lpm_add_sub:159|addcore:adder|
|lpm_add_sub:159|addcore:adder|addcore:adder0|
|lpm_add_sub:159|altshift:result_ext_latency_ffs|
|lpm_add_sub:159|altshift:carry_ext_latency_ffs|
|lpm_add_sub:159|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:227|
|lpm_add_sub:227|addcore:adder|
|lpm_add_sub:227|addcore:adder|addcore:adder0|
|lpm_add_sub:227|altshift:result_ext_latency_ffs|
|lpm_add_sub:227|altshift:carry_ext_latency_ffs|
|lpm_add_sub:227|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:503|
|lpm_add_sub:503|addcore:adder|
|lpm_add_sub:503|addcore:adder|addcore:adder0|
|lpm_add_sub:503|altshift:result_ext_latency_ffs|
|lpm_add_sub:503|altshift:carry_ext_latency_ffs|
|lpm_add_sub:503|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:571|
|lpm_add_sub:571|addcore:adder|
|lpm_add_sub:571|addcore:adder|addcore:adder0|
|lpm_add_sub:571|altshift:result_ext_latency_ffs|
|lpm_add_sub:571|altshift:carry_ext_latency_ffs|
|lpm_add_sub:571|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:843|
|lpm_add_sub:843|addcore:adder|
|lpm_add_sub:843|addcore:adder|addcore:adder0|
|lpm_add_sub:843|altshift:result_ext_latency_ffs|
|lpm_add_sub:843|altshift:carry_ext_latency_ffs|
|lpm_add_sub:843|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:902|
|lpm_add_sub:902|addcore:adder|
|lpm_add_sub:902|addcore:adder|addcore:adder0|
|lpm_add_sub:902|altshift:result_ext_latency_ffs|
|lpm_add_sub:902|altshift:carry_ext_latency_ffs|
|lpm_add_sub:902|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
***** Logic for device 'run_watch' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
m m s
i r s i e
n e t c c
_ s a V G G G c G _ _
0 e r C N N N l N 1 0
0 t t C D D D k D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
min_01 | 7 39 | sec_01
sec_00 | 8 38 | sec_03
min_02 | 9 37 | mic_12
GND | 10 36 | sec_11
min_03 | 11 35 | VCC
min_13 | 12 EPM7032LC44-6 34 | mic_11
RESERVED | 13 33 | sec_10
min_10 | 14 32 | mic_01
VCC | 15 31 | mic_02
mic_00 | 16 30 | GND
min_12 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R m G V m s m s R
E E E i N C i e i e E
S S S n D C c c c c S
E E E _ _ _ _ _ E
R R R 1 1 1 0 1 R
V V V 1 0 2 3 3 V
E E E E
D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 12/16( 75%) 3/16( 18%) 12/36( 33%)
B: LC17 - LC32 16/16(100%) 14/16( 87%) 5/16( 31%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 26/32 ( 81%)
Total shareable expanders used: 4/32 ( 12%)
Total Turbo logic cells used: 26/32 ( 81%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 8.42
Total fan-in: 219
Total input pins required: 3
Total output pins required: 24
Total bidirectional pins required: 0
Total logic cells required: 26
Total flipflops required: 26
Total product terms required: 94
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
5 (2) (A) INPUT 0 0 0 0 0 24 2 reset
4 (1) (A) INPUT 0 0 0 0 0 24 2 start
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
16 11 A FF + t 0 0 0 2 0 7 1 mic_00 (:32)
32 25 B FF + t 0 0 0 2 4 7 1 mic_01 (:31)
31 26 B FF + t 0 0 0 2 2 6 1 mic_02 (:30)
26 30 B FF + t 0 0 0 2 4 6 1 mic_03 (:29)
24 32 B FF + t 0 0 0 2 4 3 1 mic_10 (:36)
34 23 B FF + t 0 0 0 2 8 3 1 mic_11 (:35)
37 21 B FF + t 0 0 0 2 8 3 1 mic_12 (:34)
41 17 B FF + t 0 0 0 2 7 2 1 mic_13 (:33)
6 3 A FF t 0 0 0 2 1 7 0 min_00 (:49)
7 4 A FF t 1 0 1 2 5 7 0 min_01 (:48)
9 6 A FF t 0 0 0 2 3 6 0 min_02 (:47)
11 7 A FF t 0 0 0 2 5 6 0 min_03 (:46)
14 10 A FF t 0 0 0 2 5 3 0 min_10 (:53)
21 16 A FF t 1 0 1 2 9 3 0 min_11 (:52)
17 12 A FF t 0 0 0 2 9 3 0 min_12 (:51)
12 8 A FF t 1 0 0 2 9 3 0 min_13 (:50)
8 5 A FF t 0 0 0 2 1 7 1 sec_00 (:40)
39 19 B FF t 1 0 1 2 5 7 1 sec_01 (:39)
40 18 B FF t 0 0 0 2 3 6 1 sec_02 (:38)
38 20 B FF t 0 0 0 2 5 6 1 sec_03 (:37)
33 24 B FF t 0 0 0 2 5 3 1 sec_10 (:44)
36 22 B FF t 1 0 1 2 9 3 1 sec_11 (:43)
25 31 B FF t 0 0 0 2 9 3 1 sec_12 (:42)
27 29 B FF t 1 0 0 2 9 3 1 sec_13 (:41)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(29) 27 B TFFE + t 1 0 0 2 9 8 2 mic (:28)
(28) 28 B TFFE t 1 0 0 2 10 8 1 sec (:45)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC11 mic_00
| +----------------- LC3 min_00
| | +--------------- LC4 min_01
| | | +------------- LC6 min_02
| | | | +----------- LC7 min_03
| | | | | +--------- LC10 min_10
| | | | | | +------- LC16 min_11
| | | | | | | +----- LC12 min_12
| | | | | | | | +--- LC8 min_13
| | | | | | | | | +- LC5 sec_00
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC3 -> - * * * * * * * * - | * - | <-- min_00
LC4 -> - - * * * * * * * - | * - | <-- min_01
LC6 -> - - * * * * * * * - | * - | <-- min_02
LC7 -> - - * - * * * * * - | * - | <-- min_03
LC10 -> - - - - - * * * * - | * - | <-- min_10
LC16 -> - - - - - - * * * - | * - | <-- min_11
LC12 -> - - - - - - * * * - | * - | <-- min_12
LC8 -> - - - - - - * * * - | * - | <-- min_13
Pin
43 -> - - - - - - - - - - | - - | <-- clk
5 -> * * * * * * * * * * | * * | <-- reset
4 -> * * * * * * * * * * | * * | <-- start
LC27 -> - - - - - - - - - * | * * | <-- mic
LC28 -> - * * * * * * * * - | * * | <-- sec
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\run_watch\run_watch.rpt
run_watch
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
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