📄 ask.rpt
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Pin
5 -> * - - - - - - - - | * - | <-- base_input
43 -> - - - - - - - - - | - - | <-- clk
4 -> - - - - * * * * * | * * | <-- start
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\ask\ask.rpt
ask
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC23 |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
| +----------------------- LC24 |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
| | +--------------------- LC29 |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
| | | +------------------- LC30 |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node5
| | | | +----------------- LC26 |ask_decoder:u2|cnt5
| | | | | +--------------- LC22 |ask_decoder:u2|cnt4
| | | | | | +------------- LC21 |ask_decoder:u2|cnt3
| | | | | | | +----------- LC20 |ask_decoder:u2|cnt2
| | | | | | | | +--------- LC19 |ask_decoder:u2|cnt1
| | | | | | | | | +------- LC18 |ask_decoder:u2|cnt0
| | | | | | | | | | +----- LC27 |ask_decoder:u2|rising_cnt1
| | | | | | | | | | | +--- LC25 |ask_decoder:u2|rising_cnt0
| | | | | | | | | | | | +- LC17 base_output
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC23 -> - - - - - - - * - - - - - | - * | <-- |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
LC24 -> - - - - - - * - - - - - - | - * | <-- |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
LC29 -> - - - - - * - - - - - - - | - * | <-- |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
LC30 -> - - - - * - - - - - - - - | - * | <-- |ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node5
LC26 -> - - - * * * * * - - * * * | - * | <-- |ask_decoder:u2|cnt5
LC22 -> - - * * * * * * - - * * * | - * | <-- |ask_decoder:u2|cnt4
LC21 -> - * * * * * * * - - * * * | - * | <-- |ask_decoder:u2|cnt3
LC20 -> * * * * * * * * - - * * * | - * | <-- |ask_decoder:u2|cnt2
LC19 -> * * * * * * * * * - * * * | - * | <-- |ask_decoder:u2|cnt1
LC18 -> * * * * * * * * * * * * * | - * | <-- |ask_decoder:u2|cnt0
LC27 -> - - - - - - - - - - * - * | - * | <-- |ask_decoder:u2|rising_cnt1
LC25 -> - - - - - - - - - - * * * | - * | <-- |ask_decoder:u2|rising_cnt0
LC17 -> - - - - - - - - - - - - * | - * | <-- base_output
Pin
43 -> - - - - - - - - - - - - - | - - | <-- clk
4 -> - - - - * * * * * * - - - | * * | <-- start
LC15 -> - - - - - - - - - - * * - | - * | <-- |ask_decoder:u2|data_reg
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\ask\ask.rpt
ask
** EQUATIONS **
base_input : INPUT;
clk : INPUT;
start : INPUT;
-- Node name is 'ask' = '|ask_encoder:u1|:4'
-- Equation name is 'ask', type is output
ask = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = base_input & _LC004;
-- Node name is 'base_output' = '|ask_decoder:u2|:4'
-- Equation name is 'base_output', type is output
base_output = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = base_output & !_LC018 & !_LC019 & _LC020 & _LC021 & _LC022 &
!_LC025 & !_LC026 & !_LC027
# !base_output & !_LC018 & !_LC019 & _LC020 & _LC021 & _LC022 &
_LC025 & !_LC026
# !base_output & !_LC018 & !_LC019 & _LC020 & _LC021 & _LC022 &
!_LC026 & _LC027;
-- Node name is '|ask_decoder:u2|:12' = '|ask_decoder:u2|cnt0'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _EQ003 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC018 & start;
-- Node name is '|ask_decoder:u2|:11' = '|ask_decoder:u2|cnt1'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE( _EQ004 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC018 & _LC019 & start
# !_LC018 & !_LC019 & start;
-- Node name is '|ask_decoder:u2|:10' = '|ask_decoder:u2|cnt2'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _EQ005 $ _LC023, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC023 &
_LC026
# _LC023 & !start;
-- Node name is '|ask_decoder:u2|:9' = '|ask_decoder:u2|cnt3'
-- Equation name is '_LC021', type is buried
_LC021 = DFFE( _EQ006 $ _LC024, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC024 &
_LC026
# _LC024 & !start;
-- Node name is '|ask_decoder:u2|:8' = '|ask_decoder:u2|cnt4'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _EQ007 $ _LC029, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC026 &
_LC029
# _LC029 & !start;
-- Node name is '|ask_decoder:u2|:7' = '|ask_decoder:u2|cnt5'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ008 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC026 & start
# !_LC030 & start;
-- Node name is '|ask_decoder:u2|:6' = '|ask_decoder:u2|data_reg'
-- Equation name is '_LC015', type is buried
_LC015 = DFFE( ask $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( _LC020 $ _EQ009);
_EQ009 = _LC018 & _LC019;
-- Node name is '|ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _LC021 $ _EQ010);
_EQ010 = _LC018 & _LC019 & _LC020;
-- Node name is '|ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( _LC022 $ _EQ011);
_EQ011 = _LC018 & _LC019 & _LC020 & _LC021;
-- Node name is '|ask_decoder:u2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( _LC026 $ _EQ012);
_EQ012 = _LC018 & _LC019 & _LC020 & _LC021 & _LC022;
-- Node name is '|ask_decoder:u2|:14' = '|ask_decoder:u2|rising_cnt0'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( VCC, _LC015, !_EQ013, VCC, VCC);
_EQ013 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC026;
-- Node name is '|ask_decoder:u2|:13' = '|ask_decoder:u2|rising_cnt1'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( _LC025, _LC015, !_EQ014, VCC, VCC);
_EQ014 = _LC018 & _LC019 & !_LC020 & !_LC021 & !_LC022 & _LC026;
-- Node name is '|ask_encoder:u1|:9' = '|ask_encoder:u1|cntf0'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _EQ015 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC008 & start;
-- Node name is '|ask_encoder:u1|:8' = '|ask_encoder:u1|cntf1'
-- Equation name is '_LC010', type is buried
_LC010 = DFFE( _EQ016 $ start, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC008 & _LC010 & start
# !_LC008 & !_LC010 & start;
-- Node name is '|ask_encoder:u1|:7' = '|ask_encoder:u1|cntf2'
-- Equation name is '_LC011', type is buried
_LC011 = TFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC008 & _LC010 & !_LC011 & !_LC012 & start
# _LC008 & _LC010 & _LC011
# _LC011 & !start;
-- Node name is '|ask_encoder:u1|:6' = '|ask_encoder:u1|cntf3'
-- Equation name is '_LC012', type is buried
_LC012 = DFFE( _EQ018 $ _LC013, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC008 & !_LC010 & !_LC011 & !_LC012 & !_LC013 & _LC014 & start
# _LC008 & !_LC010 & !_LC011 & !_LC012 & _LC013 & !_LC014
# _LC008 & _LC010 & !_LC011 & _LC012 & _LC013
# _LC013 & !start;
-- Node name is '|ask_encoder:u1|:10' = '|ask_encoder:u1|f'
-- Equation name is '_LC004', type is buried
_LC004 = TFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = _LC004 & _LC008 & _LC010 & !_LC011 & _LC012 & start
# !_LC004 & _LC008 & !_LC010 & !_LC011 & !_LC012 & start;
-- Node name is '|ask_encoder:u1|LPM_ADD_SUB:87|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC014', type is buried
_LC014 = LCELL( _LC012 $ _EQ020);
_EQ020 = _LC008 & _LC010 & _LC011;
-- Node name is '|ask_encoder:u1|LPM_ADD_SUB:128|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( _LC012 $ _EQ021);
_EQ021 = _LC008 & _LC010 & _LC011;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl\ask\ask.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,965K
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