ask_encoder.vhd

来自「提供一个把通信中ASK调制用VHDL来实现的例子」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ask_encoder is 
  port(clk: in std_logic; --系统时钟 
       base_input: in std_logic; --基带信号
       start: in std_logic; --启动信号 
       ask_output: out std_logic); --已调信号
end ask_encoder;

architecture behav of ask_encoder is
  signal cntf: integer range 0 to 11; --载波信号f的分频计数器
  signal f: std_logic; --载波信号f
begin
  fenpin: process (clk) --此进程通过对系统时钟clk的分频，得到载波f
  begin
    if clk'event and clk='1' then
       if start='0' then
          cntf <= 0;
       elsif cntf=1 then
          f <= '1';
          cntf <= cntf + 1; 
       elsif cntf=11 then
          f <= '0';
          cntf <= 0; 
       else
          cntf <= cntf + 1;
       end if;
    end if;
  end process fenpin;
  ask_mod:process (clk) --此进程完成对基带信号的aSK调制
  begin
    if clk'event and clk='1' then 
       ask_output <= f and base_input;
    else
       null;
    end if;
  end process ask_mod;
end behav;