y.vhd

智能控制交通灯。分主路辅路

library ieee;
use ieee.std_logic_1164.all;

entity y is
  port(  y_in:in std_logic;
         clk_y:in std_logic;
         y_out:buffer std_logic
       );
end entity;

architecture bhv of y is

--signal y_temp : std_logic;

begin
  process  
    begin   
      if y_in = '1' then 
        y_out <= clk_y;   
      else  
        y_out <= '0';   
      end if;   
  end process;  
end bhv;