display.vhd

来自「智能控制交通灯。分主路辅路」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity display is
  port (  clk_d :in std_logic;
          qtime_d :in std_logic_vector(4 downto 0);
          snum_d : in std_logic_vector(1 downto 0);
          MR_d,MY_d,MG_d,CR_d,CY_d,CG_d : out std_logic;
          timebin : out std_logic_vector(4 downto 0));
end display;

architecture bhv of display is

begin
  process(clk_d)
  begin
    case snum_d is
      when "00"=> MR_d<='0';MY_d<='0';MG_d<='1';CR_d<='1';CY_d<='0';CG_d<='0';
        timebin<="00000";
      when "01"=> MR_d<='0';MY_d<='1';MG_d<='0';CR_d<='1';CY_d<='0';CG_d<='0';
        timebin<=4 - qtime_d;
      when "10"=> MR_d<='1';MY_d<='0';MG_d<='0';CR_d<='0';CY_d<='0';CG_d<='1';
        timebin<=20 - qtime_d;
      when "11"=> MR_d<='1';MY_d<='0';MG_d<='0';CR_d<='0';CY_d<='1';CG_d<='0';
        timebin<=4 - qtime_d;
      when others=>NULL;
    end case;
  end process;
end bhv;