📄 bin2seg.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bin2seg is
port ( timebin_in : in std_logic_vector(4 downto 0);
timeseg_l : out std_logic_vector(6 downto 0));
end bin2seg;
architecture bhv of bin2seg is
begin
process(timebin_in)
begin
if timebin_in<="01001" then
timeseg_l(3 downto 0)<=timebin_in;
timeseg_l(6 downto 4)<="000";
elsif timebin_in<="10011" then
timeseg_l(3 downto 0)<=timebin_in - 10;
timeseg_l(6 downto 4)<="001";
else
timeseg_l(3 downto 0)<=timebin_in - 20;
timeseg_l(6 downto 4)<="010";
end if;
end process;
end bhv;
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