clock.vhd

来自「智能控制交通灯。分主路辅路」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock is
  port(  clk_clk : in std_logic;
         clr_clk : in std_logic;
         qtime : out std_logic_vector(4 downto 0));
end;

architecture bhv of clock is
signal count : std_logic_vector(4 downto 0):="00000";
begin
  process(clk_clk,clr_clk)
  begin
    wait until rising_edge(clk_clk);
    if clr_clk='0' then
      count<=count+1;
    else
      count<="00000";
    end if;
  end process;
  qtime<=count;
end bhv;