controlm.vhd

智能控制交通灯。分主路辅路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity controlm is
  port (  s_c,clk_c :in std_logic;
          qtime_c :in std_logic_vector(4 downto 0);
          snum : out std_logic_vector(1 downto 0);
          clr : out std_logic);
end controlm;

architecture bhv of controlm is

type states is (st0,st1,st2,st3);
signal current_state,next_state: states :=st0;
begin
  com:process(s_c,qtime_c)
  begin
    clr <= '0';
	case current_state is
      when st0=> snum<="00"; 

	  if (s_c='1') then 
        if (qtime_c="00100") then
	      next_state<=st1;
	      clr <= '1';
        else
          next_state<=st0;
        end if;
      else
        next_state<=st0;
	  end if;

	
	when st1=> snum<="01"; 
      clr<='0'; 
	  if (qtime_c<"00100") then
	    next_state<=st1;
	  else 
	    next_state<=st2;
      clr<='1'; 
	  end if;


    when st2=> snum<="10"; 
      clr<='0'; 
      if (s_c='0') then
        if  qtime_c>="00101" then
          next_state<=st3;
          clr<='1';
        else
          next_state<=st2;
        end if;
      else
        if qtime_c>="10100" then
          next_state<=st3;
          clr<='1';
        else
          next_state<=st2;
        end if;
      end if;

	when st3=>  snum<="11"; 
      clr<='0';
	  if (qtime_c>="00100") then
	    next_state<=st0;
        clr<='1';
      else
        next_state<=st3;
	  end if;

	when others=>next_state<=st0;
	current_state<=next_state;
end case;
end process;

regggg : process(clk_c)
begin
  if (clk_c'event and clk_c='1') then 
	current_state<=next_state;
  end if;
end process;
end bhv;