tlight.vhd

智能控制交通灯。分主路辅路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tlight is
  port(   clk : in std_logic;
          s : in std_logic;
        mr,my,mg,cr,cy,cg:OUT STD_LOGIC;
         time_l : out std_logic_vector(6 downto 0));
end tlight;

architecture behav of tlight is

component clock
  port(  clk_clk : in std_logic;
         clr_clk : in std_logic;
         qtime : out std_logic_vector(4 downto 0));
end component;

component controlm
  port (  s_c,clk_c :in std_logic;
          qtime_c :in std_logic_vector(4 downto 0);
          snum : out std_logic_vector(1 downto 0);
          clr : out std_logic);
end component;

component display
  port (  clk_d :in std_logic;
          qtime_d :in std_logic_vector(4 downto 0);
          snum_d : in std_logic_vector(1 downto 0);
          MR_d,MY_d,MG_d,CR_d,CY_d,CG_d : out std_logic;
          timebin : out std_logic_vector(4 downto 0));
end component;

component y is
  port(  Y_in:in std_logic;
         clk_y:in std_logic;
         Y_out:out std_logic);
end component;

component bin2seg
  port (  timebin_in : in std_logic_vector(4 downto 0);
          timeseg_l : out std_logic_vector(6 downto 0));
end component;
 
signal clr_wire : std_logic;
signal qtime_wire,timebin_wire : std_logic_vector(4 downto 0);
signal timeseg_l_wire,timeseg_h_wire : std_logic_vector(4 downto 0);
signal snum_wire : std_logic_vector(1 downto 0);
signal MY_wire,CY_wire : std_logic;

begin
u1: clock port map(clk_clk=>clk,clr_clk=>clr_wire,qtime=>qtime_wire);
u2: controlm port map(clk_c=>clk,s_c=>s,qtime_c=>qtime_wire,clr=>clr_wire,snum=>snum_wire);
u3: display port map(clk_d=>clk,qtime_d=>qtime_wire,snum_d=>snum_wire,timebin=>timebin_wire,MR_d=>MR,MY_d=>MY_wire,MG_d=>MG,CR_d=>CR,CY_d=>CY_wire,CG_d=>CG);
u4: bin2seg port map(timebin_in=>timebin_wire,timeseg_l=>time_l);
u5: y port map(Y_in=>MY_wire,clk_y=>clk,Y_out=>MY);
u6: y port map(Y_in=>CY_wire,clk_y=>clk,Y_out=>CY);
end behav;