max3490.v

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· Verilog 代码 · 共 189 行

///////////////////////////////////////////////////////////////////////////////////////
//Company      : 伟杰电子                                                            //                  
//Web address  : http://www.weijay.com                                               //
//Engineer     : Jaylee                                                              //
//Email        : [e-mail]                                                 //
//实验名称     : RS485收发实验                                                       //
//功能实现     ：在LED上显示收发的数据（左边发送的数据，右边接受的数据               //
//功能实现     ：D7,D6,D5分别为收发错误状态指示。D7(接收到的数据全为0                //
//功能实现     ：包括（起始,数据,停止位)D6(停止位出错）D5（起始位出错)               //                    //
///////////////////////////////////////////////////////////////////////////////////////                                                     
//------------------------------------system clk 50MHz-------------------------------//
module MAX3490(
               clk,
               rst_n,
               max3490_txd,
               max3490_rxd,
               CH451_DCLK,
               CH451_DIN,
               CH451_LOAD,
               error_under_run,
               error_all_low,
               error_over_run
              );

input          clk;
input          rst_n;
input          max3490_rxd;

output         max3490_txd;
output         CH451_DCLK;
output         CH451_DIN;
output         CH451_LOAD;

output         error_under_run;
output         error_all_low;
output         error_over_run;



parameter      MAX3490_idle                  = 6'b000001,
               MAX3490_start                 = 6'b000010,
               MAX3490_sending               = 6'b000100,
               MAX3490_reading               = 6'b001000,
               MAX3490_waiting               = 6'b010000,
               MAX3490_delay                 = 6'b100000;

reg[5:0]       state;
reg[2:0]       counter1;
reg[2:0]       counter2;
reg[23:0]      counter3;
reg[19:0]      counter4;
reg[7:0]       write_data;
reg[7:0]       read_data;
reg[15:0]      display_data;
reg            load;
reg            rd;



wire            serial_clk_16x;
wire[7:0]       recv_data;
wire            data_ready;
wire            error_over_run;
wire            error_under_run;
wire            error_all_low;
wire            load_request;

always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    counter1<=0;
    counter2<=0;
    counter3<=0;
    counter4<=0;
    load<=1'b0;
    rd<=1'b0;
    write_data<=0;
    read_data<=0;
    display_data<=0;
    state<=MAX3490_idle;
  end
  else begin
  case(state)
  MAX3490_idle:begin            //上电等待MAX3490芯片初始化
    load<=1'b0;
    rd<=1'b0;
    if(counter4==20'hfffff) begin
      state<=MAX3490_start;
      counter4<=0;
    end
    else begin
      counter4<=counter4+1'b1;
      state<=MAX3490_idle;
    end
  end
  MAX3490_start:begin
    if(load_request==1) state<=MAX3490_sending;
    else state<=MAX3490_start;
  end
  MAX3490_sending:begin
    load<=1'b1;
    if(counter1==7) begin
      counter1<=0;
      load<=1'b0;
      state<=MAX3490_reading;
    end
    else begin
      counter1<=counter1+1'b1;
      state<=MAX3490_sending;
    end
  end
  MAX3490_reading:begin
    if(data_ready==1) begin
	  rd<=1;
	  read_data<=recv_data;
	  state<=MAX3490_waiting;
	end
	else state<=MAX3490_reading;
  end
  MAX3490_waiting:begin
    if(counter2==7)begin
      display_data<={write_data,read_data};
      state<=MAX3490_delay;
      counter2<=0;
      write_data<=write_data+1'b1;
      rd<=1'b0;
    end
    else begin
      counter2<=counter2+1'b1;
      state<=MAX3490_waiting;
    end
  end
  MAX3490_delay:begin
    if(counter3==24'hffffff) begin
      counter3<=0;
      state<=MAX3490_start;
    end
    else begin
      counter3<=counter3+1'b1;
      state<=MAX3490_delay;
    end
  end
  default:state<=MAX3490_idle;
  endcase
  end
end


rs232rx    m1  (
                .clk(clk),
                .rx_clk(serial_clk_16x),
                .reset(!rst_n),
                .rxd(max3490_rxd),
                .read(rd),
               . data(recv_data),
                .data_ready(data_ready),
                .error_over_run(error_over_run),
                .error_under_run(error_under_run),
                .error_all_low(error_all_low)
                );

rs232tx   m2   (
                .clk(clk),
                .tx_clk(serial_clk_16x),
                .reset(!rst_n),
                .load(load),
                .data(write_data),
                .load_request(load_request),
                .txd(max3490_txd)
                );


clock_gen_select   m3   (
                         .clk(clk),
                         .reset(!rst_n),
                         .rate_select(3'b100),
                         .clk_out(serial_clk_16x)
                         );

DISPLAY    m4  (
                .clk(clk),
                .rst_n(rst_n),
                .data({display_data[15:8],16'h0000,display_data[7:0]}),
                .CH451_DCLK(CH451_DCLK),
                .CH451_DIN(CH451_DIN),
                .CH451_LOAD(CH451_LOAD)
               );

endmodule