max3490.tan.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "rs232rx:m1\|q\[9\] max3490_rxd clk 5.838 ns register " "Info: tsu for register \"rs232rx:m1\|q\[9\]\" (data pin = \"max3490_rxd\", clock pin = \"clk\") is 5.838 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.743 ns + Longest pin register " "Info: + Longest pin to register delay is 8.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns max3490_rxd 1 PIN PIN_158 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 5; PIN Node = 'max3490_rxd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { max3490_rxd } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.796 ns) + CELL(0.478 ns) 8.743 ns rs232rx:m1\|q\[9\] 2 REG LC_X21_Y10_N9 5 " "Info: 2: + IC(6.796 ns) + CELL(0.478 ns) = 8.743 ns; Loc. = LC_X21_Y10_N9; Fanout = 5; REG Node = 'rs232rx:m1\|q\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.274 ns" { max3490_rxd rs232rx:m1|q[9] } "NODE_NAME" } } { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 213 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 22.27 % ) " "Info: Total cell delay = 1.947 ns ( 22.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.796 ns ( 77.73 % ) " "Info: Total interconnect delay = 6.796 ns ( 77.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.743 ns" { max3490_rxd rs232rx:m1|q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.743 ns" { max3490_rxd max3490_rxd~out0 rs232rx:m1|q[9] } { 0.000ns 0.000ns 6.796ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 213 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 271 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 271; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns rs232rx:m1\|q\[9\] 2 REG LC_X21_Y10_N9 5 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y10_N9; Fanout = 5; REG Node = 'rs232rx:m1\|q\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk rs232rx:m1|q[9] } "NODE_NAME" } } { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 213 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk rs232rx:m1|q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 rs232rx:m1|q[9] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.743 ns" { max3490_rxd rs232rx:m1|q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.743 ns" { max3490_rxd max3490_rxd~out0 rs232rx:m1|q[9] } { 0.000ns 0.000ns 6.796ns } { 0.000ns 1.469ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk rs232rx:m1|q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 rs232rx:m1|q[9] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk max3490_txd rs232tx:m2\|q\[0\] 8.566 ns register " "Info: tco from clock \"clk\" to destination pin \"max3490_txd\" through register \"rs232tx:m2\|q\[0\]\" is 8.566 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.913 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 271 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 271; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.711 ns) 2.913 ns rs232tx:m2\|q\[0\] 2 REG LC_X19_Y8_N1 2 " "Info: 2: + IC(0.733 ns) + CELL(0.711 ns) = 2.913 ns; Loc. = LC_X19_Y8_N1; Fanout = 2; REG Node = 'rs232tx:m2\|q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.444 ns" { clk rs232tx:m2|q[0] } "NODE_NAME" } } { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.84 % ) " "Info: Total cell delay = 2.180 ns ( 74.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.733 ns ( 25.16 % ) " "Info: Total interconnect delay = 0.733 ns ( 25.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk rs232tx:m2|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 rs232tx:m2|q[0] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.429 ns + Longest register pin " "Info: + Longest register to pin delay is 5.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232tx:m2\|q\[0\] 1 REG LC_X19_Y8_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y8_N1; Fanout = 2; REG Node = 'rs232tx:m2\|q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rs232tx:m2|q[0] } "NODE_NAME" } } { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.305 ns) + CELL(2.124 ns) 5.429 ns max3490_txd 2 PIN PIN_156 0 " "Info: 2: + IC(3.305 ns) + CELL(2.124 ns) = 5.429 ns; Loc. = PIN_156; Fanout = 0; PIN Node = 'max3490_txd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.429 ns" { rs232tx:m2|q[0] max3490_txd } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 39.12 % ) " "Info: Total cell delay = 2.124 ns ( 39.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.305 ns ( 60.88 % ) " "Info: Total interconnect delay = 3.305 ns ( 60.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.429 ns" { rs232tx:m2|q[0] max3490_txd } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.429 ns" { rs232tx:m2|q[0] max3490_txd } { 0.000ns 3.305ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk rs232tx:m2|q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 rs232tx:m2|q[0] } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.429 ns" { rs232tx:m2|q[0] max3490_txd } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.429 ns" { rs232tx:m2|q[0] max3490_txd } { 0.000ns 3.305ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "rs232rx:m1\|data\[3\] rst_n clk -0.166 ns register " "Info: th for register \"rs232rx:m1\|data\[3\]\" (data pin = \"rst_n\", clock pin = \"clk\") is -0.166 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 271 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 271; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns rs232rx:m1\|data\[3\] 2 REG LC_X20_Y12_N9 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y12_N9; Fanout = 1; REG Node = 'rs232rx:m1\|data\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk rs232rx:m1|data[3] } "NODE_NAME" } } { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk rs232rx:m1|data[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 rs232rx:m1|data[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 226 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.123 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst_n 1 PIN PIN_29 246 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 246; PIN Node = 'rst_n'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.345 ns) + CELL(0.309 ns) 3.123 ns rs232rx:m1\|data\[3\] 2 REG LC_X20_Y12_N9 1 " "Info: 2: + IC(1.345 ns) + CELL(0.309 ns) = 3.123 ns; Loc. = LC_X20_Y12_N9; Fanout = 1; REG Node = 'rs232rx:m1\|data\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.654 ns" { rst_n rs232rx:m1|data[3] } "NODE_NAME" } } { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 56.93 % ) " "Info: Total cell delay = 1.778 ns ( 56.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.345 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.345 ns ( 43.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.123 ns" { rst_n rs232rx:m1|data[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.123 ns" { rst_n rst_n~out0 rs232rx:m1|data[3] } { 0.000ns 0.000ns 1.345ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk rs232rx:m1|data[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 rs232rx:m1|data[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.123 ns" { rst_n rs232rx:m1|data[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.123 ns" { rst_n rst_n~out0 rs232rx:m1|data[3] } { 0.000ns 0.000ns 1.345ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 30 00:04:27 2008 " "Info: Processing ended: Mon Jun 30 00:04:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}