max3490.tan.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 30 00:04:27 2008 " "Info: Processing started: Mon Jun 30 00:04:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off MAX3490 -c MAX3490 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MAX3490 -c MAX3490 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter4\[8\] register state.MAX3490_start 179.73 MHz 5.564 ns Internal " "Info: Clock \"clk\" has Internal fmax of 179.73 MHz between source register \"counter4\[8\]\" and destination register \"state.MAX3490_start\" (period= 5.564 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.291 ns + Longest register register " "Info: + Longest register to register delay is 5.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter4\[8\] 1 REG LC_X16_Y12_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N8; Fanout = 4; REG Node = 'counter4\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter4[8] } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.314 ns) + CELL(0.590 ns) 1.904 ns Equal0~204 2 COMB LC_X16_Y10_N9 1 " "Info: 2: + IC(1.314 ns) + CELL(0.590 ns) = 1.904 ns; Loc. = LC_X16_Y10_N9; Fanout = 1; COMB Node = 'Equal0~204'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.904 ns" { counter4[8] Equal0~204 } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.590 ns) 2.922 ns Equal0~206 3 COMB LC_X16_Y10_N6 2 " "Info: 3: + IC(0.428 ns) + CELL(0.590 ns) = 2.922 ns; Loc. = LC_X16_Y10_N6; Fanout = 2; COMB Node = 'Equal0~206'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.018 ns" { Equal0~204 Equal0~206 } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.762 ns) + CELL(0.607 ns) 5.291 ns state.MAX3490_start 4 REG LC_X21_Y8_N7 3 " "Info: 4: + IC(1.762 ns) + CELL(0.607 ns) = 5.291 ns; Loc. = LC_X21_Y8_N7; Fanout = 3; REG Node = 'state.MAX3490_start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.369 ns" { Equal0~206 state.MAX3490_start } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.787 ns ( 33.77 % ) " "Info: Total cell delay = 1.787 ns ( 33.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.504 ns ( 66.23 % ) " "Info: Total interconnect delay = 3.504 ns ( 66.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.291 ns" { counter4[8] Equal0~204 Equal0~206 state.MAX3490_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.291 ns" { counter4[8] Equal0~204 Equal0~206 state.MAX3490_start } { 0.000ns 1.314ns 0.428ns 1.762ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.913 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 271 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 271; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.711 ns) 2.913 ns state.MAX3490_start 2 REG LC_X21_Y8_N7 3 " "Info: 2: + IC(0.733 ns) + CELL(0.711 ns) = 2.913 ns; Loc. = LC_X21_Y8_N7; Fanout = 3; REG Node = 'state.MAX3490_start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.444 ns" { clk state.MAX3490_start } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.84 % ) " "Info: Total cell delay = 2.180 ns ( 74.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.733 ns ( 25.16 % ) " "Info: Total interconnect delay = 0.733 ns ( 25.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk state.MAX3490_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 state.MAX3490_start } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 271 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 271; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns counter4\[8\] 2 REG LC_X16_Y12_N8 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y12_N8; Fanout = 4; REG Node = 'counter4\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.456 ns" { clk counter4[8] } "NODE_NAME" } } { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk counter4[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 counter4[8] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk state.MAX3490_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 state.MAX3490_start } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk counter4[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 counter4[8] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 69 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 47 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.291 ns" { counter4[8] Equal0~204 Equal0~206 state.MAX3490_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.291 ns" { counter4[8] Equal0~204 Equal0~206 state.MAX3490_start } { 0.000ns 1.314ns 0.428ns 1.762ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk state.MAX3490_start } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 state.MAX3490_start } { 0.000ns 0.000ns 0.733ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk counter4[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 counter4[8] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}