max3490.fit.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 38 行 · 第 1/2 页

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.760 ns register register " "Info: Estimated most critical path is register to register delay of 4.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DISPLAY:m4\|shift_counter\[1\] 1 REG LAB_X19_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y14; Fanout = 4; REG Node = 'DISPLAY:m4\|shift_counter\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DISPLAY:m4|shift_counter[1] } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.590 ns) 0.975 ns DISPLAY:m4\|Equal1~122 2 COMB LAB_X20_Y14 3 " "Info: 2: + IC(0.385 ns) + CELL(0.590 ns) = 0.975 ns; Loc. = LAB_X20_Y14; Fanout = 3; COMB Node = 'DISPLAY:m4\|Equal1~122'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.975 ns" { DISPLAY:m4|shift_counter[1] DISPLAY:m4|Equal1~122 } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.592 ns) + CELL(0.114 ns) 1.681 ns DISPLAY:m4\|Equal1~123 3 COMB LAB_X20_Y14 3 " "Info: 3: + IC(0.592 ns) + CELL(0.114 ns) = 1.681 ns; Loc. = LAB_X20_Y14; Fanout = 3; COMB Node = 'DISPLAY:m4\|Equal1~123'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.706 ns" { DISPLAY:m4|Equal1~122 DISPLAY:m4|Equal1~123 } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 214 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.442 ns) 2.573 ns DISPLAY:m4\|CH451_cmd\[0\]~615 4 COMB LAB_X21_Y14 1 " "Info: 4: + IC(0.450 ns) + CELL(0.442 ns) = 2.573 ns; Loc. = LAB_X21_Y14; Fanout = 1; COMB Node = 'DISPLAY:m4\|CH451_cmd\[0\]~615'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { DISPLAY:m4|Equal1~123 DISPLAY:m4|CH451_cmd[0]~615 } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 3.226 ns DISPLAY:m4\|CH451_cmd\[0\]~616 5 COMB LAB_X21_Y14 11 " "Info: 5: + IC(0.361 ns) + CELL(0.292 ns) = 3.226 ns; Loc. = LAB_X21_Y14; Fanout = 11; COMB Node = 'DISPLAY:m4\|CH451_cmd\[0\]~616'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { DISPLAY:m4|CH451_cmd[0]~615 DISPLAY:m4|CH451_cmd[0]~616 } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.867 ns) 4.760 ns DISPLAY:m4\|CH451_cmd\[3\] 6 REG LAB_X22_Y14 1 " "Info: 6: + IC(0.667 ns) + CELL(0.867 ns) = 4.760 ns; Loc. = LAB_X22_Y14; Fanout = 1; REG Node = 'DISPLAY:m4\|CH451_cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.534 ns" { DISPLAY:m4|CH451_cmd[0]~616 DISPLAY:m4|CH451_cmd[3] } "NODE_NAME" } } { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.305 ns ( 48.42 % ) " "Info: Total cell delay = 2.305 ns ( 48.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.455 ns ( 51.58 % ) " "Info: Total interconnect delay = 2.455 ns ( 51.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.760 ns" { DISPLAY:m4|shift_counter[1] DISPLAY:m4|Equal1~122 DISPLAY:m4|Equal1~123 DISPLAY:m4|CH451_cmd[0]~615 DISPLAY:m4|CH451_cmd[0]~616 DISPLAY:m4|CH451_cmd[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 3 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y11 x23_y21 " "Info: The peak interconnect region extends from location x12_y11 to location x23_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 30 00:04:21 2008 " "Info: Processing ended: Mon Jun 30 00:04:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}