max3490.fit.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 38 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 30 00:04:16 2008 " "Info: Processing started: Mon Jun 30 00:04:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off MAX3490 -c MAX3490 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off MAX3490 -c MAX3490" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "MAX3490 EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"MAX3490\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 25 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"rst_n\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|q\[0\] " "Info: Destination \"rs232tx:m2\|q\[0\]\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|q\[1\] " "Info: Destination \"rs232tx:m2\|q\[1\]\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232rx:m1\|m1_state.m1_under_run " "Info: Destination \"rs232rx:m1\|m1_state.m1_under_run\" may be non-global or may not use global clock" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 89 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232rx:m1\|m1_state.m1_all_low " "Info: Destination \"rs232rx:m1\|m1_state.m1_all_low\" may be non-global or may not use global clock" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 89 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232rx:m1\|m1_state.m1_over_run " "Info: Destination \"rs232rx:m1\|m1_state.m1_over_run\" may be non-global or may not use global clock" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 89 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_gen_select:m3\|dds_phase\[5\] " "Info: Destination \"clock_gen_select:m3\|dds_phase\[5\]\" may be non-global or may not use global clock" {  } { { "clock_gen_select.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/clock_gen_select.v" 209 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|m1_state.m1_sending_last_bit " "Info: Destination \"rs232tx:m2\|m1_state.m1_sending_last_bit\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 76 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|prescaler_count_l\[3\] " "Info: Destination \"rs232tx:m2\|prescaler_count_l\[3\]\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 96 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|prescaler_count_l\[2\] " "Info: Destination \"rs232tx:m2\|prescaler_count_l\[2\]\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 96 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rs232tx:m2\|prescaler_count_l\[1\] " "Info: Destination \"rs232tx:m2\|prescaler_count_l\[1\]\" may be non-global or may not use global clock" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 96 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 26 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}