max3490.hier_info

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· HIER_INFO 代码 · 共 426 行

|MAX3490
clk => clk~0.IN4
rst_n => rst_n~0.IN1
max3490_txd <= rs232tx:m2.txd
max3490_rxd => max3490_rxd~0.IN1
CH451_DCLK <= DISPLAY:m4.CH451_DCLK
CH451_DIN <= DISPLAY:m4.CH451_DIN
CH451_LOAD <= DISPLAY:m4.CH451_LOAD
error_under_run <= rs232rx:m1.error_under_run
error_all_low <= rs232rx:m1.error_all_low
error_over_run <= rs232rx:m1.error_over_run


|MAX3490|rs232rx:m1
clk => m2_state.CLK
clk => intrabit_count_l[3].CLK
clk => intrabit_count_l[2].CLK
clk => intrabit_count_l[1].CLK
clk => intrabit_count_l[0].CLK
clk => q[9].CLK
clk => q[8].CLK
clk => q[7].CLK
clk => q[6].CLK
clk => q[5].CLK
clk => q[4].CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => data[7]~reg0.CLK
clk => data[6]~reg0.CLK
clk => data[5]~reg0.CLK
clk => data[4]~reg0.CLK
clk => data[3]~reg0.CLK
clk => data[2]~reg0.CLK
clk => data[1]~reg0.CLK
clk => data[0]~reg0.CLK
clk => m1_state~6.IN1
rx_clk => intrabit_count_l~4.OUTPUTSELECT
rx_clk => intrabit_count_l~5.OUTPUTSELECT
rx_clk => intrabit_count_l~6.OUTPUTSELECT
rx_clk => intrabit_count_l~7.OUTPUTSELECT
rx_clk => mid_bit_l.IN0
reset => m1_state~0.OUTPUTSELECT
reset => m1_state~1.OUTPUTSELECT
reset => m1_state~2.OUTPUTSELECT
reset => m1_state~3.OUTPUTSELECT
reset => m1_state~4.OUTPUTSELECT
reset => m1_state~5.OUTPUTSELECT
reset => Selector4.IN2
reset => Selector4.IN3
reset => Selector4.IN4
reset => m2_state~0.OUTPUTSELECT
reset => data~8.OUTPUTSELECT
reset => data~9.OUTPUTSELECT
reset => data~10.OUTPUTSELECT
reset => data~11.OUTPUTSELECT
reset => data~12.OUTPUTSELECT
reset => data~13.OUTPUTSELECT
reset => data~14.OUTPUTSELECT
reset => data~15.OUTPUTSELECT
reset => Selector2.IN2
reset => Selector0.IN2
reset => Selector1.IN1
rxd => m1_state_logic~1.IN0
rxd => q~0.DATAB
rxd => Selector4.IN5
rxd => m1_state_logic~0.IN0
rxd => Selector5.IN1
read => m2_next_state.DATAB
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_ready <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
error_over_run <= m1_state.m1_over_run.DB_MAX_OUTPUT_PORT_TYPE
error_under_run <= m1_state.m1_under_run.DB_MAX_OUTPUT_PORT_TYPE
error_all_low <= m1_state.m1_all_low.DB_MAX_OUTPUT_PORT_TYPE


|MAX3490|rs232tx:m2
clk => prescaler_count_l[2].CLK
clk => prescaler_count_l[1].CLK
clk => prescaler_count_l[0].CLK
clk => tx_bit_count_l[3].CLK
clk => tx_bit_count_l[2].CLK
clk => tx_bit_count_l[1].CLK
clk => tx_bit_count_l[0].CLK
clk => data_in_waiting[7].CLK
clk => data_in_waiting[6].CLK
clk => data_in_waiting[5].CLK
clk => data_in_waiting[4].CLK
clk => data_in_waiting[3].CLK
clk => data_in_waiting[2].CLK
clk => data_in_waiting[1].CLK
clk => data_in_waiting[0].CLK
clk => q[9].CLK
clk => q[8].CLK
clk => q[7].CLK
clk => q[6].CLK
clk => q[5].CLK
clk => q[4].CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => prescaler_count_l[3].CLK
clk => m1_state~4.IN1
tx_clk => prescaler_count_l~4.OUTPUTSELECT
tx_clk => prescaler_count_l~5.OUTPUTSELECT
tx_clk => prescaler_count_l~6.OUTPUTSELECT
tx_clk => prescaler_count_l~7.OUTPUTSELECT
tx_clk => tx_clk_1x.IN1
reset => prescaler_count_l~8.OUTPUTSELECT
reset => prescaler_count_l~9.OUTPUTSELECT
reset => prescaler_count_l~10.OUTPUTSELECT
reset => prescaler_count_l~11.OUTPUTSELECT
reset => m1_state~0.OUTPUTSELECT
reset => m1_state~1.OUTPUTSELECT
reset => m1_state~2.OUTPUTSELECT
reset => m1_state~3.OUTPUTSELECT
reset => q~20.OUTPUTSELECT
reset => q~21.OUTPUTSELECT
reset => q~22.OUTPUTSELECT
reset => q~23.OUTPUTSELECT
reset => q~24.OUTPUTSELECT
reset => q~25.OUTPUTSELECT
reset => q~26.OUTPUTSELECT
reset => q~27.OUTPUTSELECT
reset => q~28.OUTPUTSELECT
reset => q~29.OUTPUTSELECT
load => start_sending~1.IN1
load => m1_next_state~1.DATAA
load => state_logic~0.IN1
load => m1_next_state~0.DATAA
load => data_in_waiting[7].ENA
load => data_in_waiting[6].ENA
load => data_in_waiting[5].ENA
load => data_in_waiting[4].ENA
load => data_in_waiting[3].ENA
load => data_in_waiting[2].ENA
load => data_in_waiting[1].ENA
load => data_in_waiting[0].ENA
data[0] => data_in_waiting[0].DATAIN
data[1] => data_in_waiting[1].DATAIN
data[2] => data_in_waiting[2].DATAIN
data[3] => data_in_waiting[3].DATAIN
data[4] => data_in_waiting[4].DATAIN
data[5] => data_in_waiting[5].DATAIN
data[6] => data_in_waiting[6].DATAIN
data[7] => data_in_waiting[7].DATAIN
load_request <= Selector0.DB_MAX_OUTPUT_PORT_TYPE
txd <= q[0].DB_MAX_OUTPUT_PORT_TYPE


|MAX3490|clock_gen_select:m3
clk => dds_prescale_count[1].CLK
clk => dds_prescale_count[0].CLK
clk => dds_phase[5].CLK
clk => dds_phase[4].CLK
clk => dds_phase[3].CLK
clk => dds_phase[2].CLK
clk => dds_phase[1].CLK
clk => dds_phase[0].CLK
clk => delayed_pulse.CLK
clk => dds_prescale_count[2].CLK
reset => dds_prescale_count~3.OUTPUTSELECT
reset => dds_prescale_count~4.OUTPUTSELECT
reset => dds_prescale_count~5.OUTPUTSELECT
reset => dds_phase~6.OUTPUTSELECT
reset => dds_phase~7.OUTPUTSELECT
reset => dds_phase~8.OUTPUTSELECT
reset => dds_phase~9.OUTPUTSELECT
reset => dds_phase~10.OUTPUTSELECT
reset => dds_phase~11.OUTPUTSELECT
rate_select[0] => Decoder0.IN2
rate_select[1] => Decoder0.IN1
rate_select[2] => Decoder0.IN0
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE


|MAX3490|DISPLAY:m4
clk => clk_div_counter[2].CLK
clk => clk_div_counter[1].CLK
clk => clk_div_counter[0].CLK
clk => CH451_DIN~reg0.CLK
clk => CH451_DCLK~reg0.CLK
clk => CH451_LOAD~reg0.CLK
clk => transfer_count[2].CLK
clk => transfer_count[1].CLK
clk => transfer_count[0].CLK
clk => shift_counter[3].CLK
clk => shift_counter[2].CLK
clk => shift_counter[1].CLK
clk => shift_counter[0].CLK
clk => display_data[31].CLK
clk => display_data[30].CLK
clk => display_data[29].CLK
clk => display_data[28].CLK
clk => display_data[27].CLK
clk => display_data[26].CLK
clk => display_data[25].CLK
clk => display_data[24].CLK
clk => display_data[23].CLK
clk => display_data[22].CLK
clk => display_data[21].CLK
clk => display_data[20].CLK
clk => display_data[19].CLK
clk => display_data[18].CLK
clk => display_data[17].CLK
clk => display_data[16].CLK
clk => display_data[15].CLK
clk => display_data[14].CLK
clk => display_data[13].CLK
clk => display_data[12].CLK
clk => display_data[11].CLK
clk => display_data[10].CLK
clk => display_data[9].CLK
clk => display_data[8].CLK
clk => display_data[7].CLK
clk => display_data[6].CLK
clk => display_data[5].CLK
clk => display_data[4].CLK
clk => display_data[3].CLK
clk => display_data[2].CLK
clk => display_data[1].CLK
clk => display_data[0].CLK
clk => decemial_point_sel[7].CLK
clk => decemial_point_sel[6].CLK
clk => decemial_point_sel[5].CLK
clk => decemial_point_sel[4].CLK
clk => decemial_point_sel[3].CLK
clk => decemial_point_sel[2].CLK
clk => decemial_point_sel[1].CLK
clk => decemial_point_sel[0].CLK
clk => display_led_sel[31].CLK
clk => display_led_sel[30].CLK
clk => display_led_sel[29].CLK
clk => display_led_sel[28].CLK
clk => display_led_sel[27].CLK
clk => display_led_sel[26].CLK
clk => display_led_sel[25].CLK
clk => display_led_sel[24].CLK
clk => display_led_sel[23].CLK
clk => display_led_sel[22].CLK
clk => display_led_sel[21].CLK
clk => display_led_sel[20].CLK
clk => display_led_sel[19].CLK
clk => display_led_sel[18].CLK
clk => display_led_sel[17].CLK
clk => display_led_sel[16].CLK
clk => display_led_sel[15].CLK
clk => display_led_sel[14].CLK
clk => display_led_sel[13].CLK
clk => display_led_sel[12].CLK
clk => display_led_sel[11].CLK
clk => display_led_sel[10].CLK
clk => display_led_sel[9].CLK
clk => display_led_sel[8].CLK
clk => display_led_sel[7].CLK
clk => display_led_sel[6].CLK
clk => display_led_sel[5].CLK
clk => display_led_sel[4].CLK
clk => display_led_sel[3].CLK
clk => display_led_sel[2].CLK
clk => display_led_sel[1].CLK
clk => display_led_sel[0].CLK
clk => CH451_cmd[11].CLK
clk => CH451_cmd[10].CLK
clk => CH451_cmd[9].CLK
clk => CH451_cmd[8].CLK
clk => CH451_cmd[7].CLK
clk => CH451_cmd[6].CLK
clk => CH451_cmd[5].CLK
clk => CH451_cmd[4].CLK
clk => CH451_cmd[3].CLK
clk => CH451_cmd[2].CLK
clk => CH451_cmd[1].CLK
clk => CH451_cmd[0].CLK
clk => trans_over_flag.CLK
clk => clk_div_counter[3].CLK
clk => state~22.IN1
clk => shift_state~15.IN1
rst_n => CH451_DIN~reg0.PRESET
rst_n => CH451_DCLK~reg0.PRESET
rst_n => CH451_LOAD~reg0.PRESET
rst_n => transfer_count[2].ACLR
rst_n => transfer_count[1].ACLR
rst_n => transfer_count[0].ACLR
rst_n => shift_counter[3].ACLR
rst_n => shift_counter[2].ACLR
rst_n => shift_counter[1].ACLR
rst_n => shift_counter[0].ACLR
rst_n => display_data[31].ACLR
rst_n => display_data[30].ACLR
rst_n => display_data[29].ACLR
rst_n => display_data[28].ACLR
rst_n => display_data[27].ACLR
rst_n => display_data[26].ACLR
rst_n => display_data[25].ACLR
rst_n => display_data[24].ACLR
rst_n => display_data[23].ACLR
rst_n => display_data[22].ACLR
rst_n => display_data[21].ACLR
rst_n => display_data[20].ACLR
rst_n => display_data[19].ACLR
rst_n => display_data[18].ACLR
rst_n => display_data[17].ACLR
rst_n => display_data[16].ACLR
rst_n => display_data[15].ACLR
rst_n => display_data[14].ACLR
rst_n => display_data[13].ACLR
rst_n => display_data[12].ACLR
rst_n => display_data[11].ACLR
rst_n => display_data[10].ACLR
rst_n => display_data[9].ACLR
rst_n => display_data[8].ACLR
rst_n => display_data[7].ACLR
rst_n => display_data[6].ACLR
rst_n => display_data[5].ACLR
rst_n => display_data[4].ACLR
rst_n => display_data[3].ACLR
rst_n => display_data[2].ACLR
rst_n => display_data[1].ACLR
rst_n => display_data[0].ACLR
rst_n => decemial_point_sel[7].ACLR
rst_n => decemial_point_sel[6].ACLR
rst_n => decemial_point_sel[5].ACLR
rst_n => decemial_point_sel[4].ACLR
rst_n => decemial_point_sel[3].ACLR
rst_n => decemial_point_sel[2].ACLR
rst_n => decemial_point_sel[1].ACLR
rst_n => decemial_point_sel[0].ACLR
rst_n => display_led_sel[31].ACLR
rst_n => display_led_sel[30].ACLR
rst_n => display_led_sel[29].ACLR
rst_n => display_led_sel[28].ACLR
rst_n => display_led_sel[27].ACLR
rst_n => display_led_sel[26].ACLR
rst_n => display_led_sel[25].ACLR
rst_n => display_led_sel[24].ACLR
rst_n => display_led_sel[23].ACLR
rst_n => display_led_sel[22].ACLR
rst_n => display_led_sel[21].ACLR
rst_n => display_led_sel[20].ACLR
rst_n => display_led_sel[19].ACLR
rst_n => display_led_sel[18].ACLR
rst_n => display_led_sel[17].ACLR
rst_n => display_led_sel[16].ACLR
rst_n => display_led_sel[15].ACLR
rst_n => display_led_sel[14].ACLR
rst_n => display_led_sel[13].ACLR
rst_n => display_led_sel[12].ACLR
rst_n => display_led_sel[11].ACLR
rst_n => display_led_sel[10].ACLR
rst_n => display_led_sel[9].ACLR
rst_n => display_led_sel[8].ACLR
rst_n => display_led_sel[7].ACLR
rst_n => display_led_sel[6].ACLR
rst_n => display_led_sel[5].ACLR
rst_n => display_led_sel[4].ACLR
rst_n => display_led_sel[3].ACLR
rst_n => display_led_sel[2].ACLR
rst_n => display_led_sel[1].ACLR
rst_n => display_led_sel[0].ACLR
rst_n => CH451_cmd[11].ACLR
rst_n => CH451_cmd[10].ACLR
rst_n => CH451_cmd[9].ACLR
rst_n => CH451_cmd[8].ACLR
rst_n => CH451_cmd[7].ACLR
rst_n => CH451_cmd[6].ACLR
rst_n => CH451_cmd[5].ACLR
rst_n => CH451_cmd[4].ACLR
rst_n => CH451_cmd[3].ACLR
rst_n => CH451_cmd[2].ACLR
rst_n => CH451_cmd[1].ACLR
rst_n => CH451_cmd[0].ACLR
rst_n => trans_over_flag.ACLR
rst_n => clk_div_counter[2].ACLR
rst_n => clk_div_counter[1].ACLR
rst_n => clk_div_counter[0].ACLR
rst_n => clk_div_counter[3].ACLR
rst_n => state~23.IN1
rst_n => shift_state~16.IN1
data[0] => Selector70.IN2
data[1] => Selector69.IN2
data[2] => Selector68.IN2
data[3] => Selector67.IN2
data[4] => Selector66.IN2
data[5] => Selector65.IN2
data[6] => Selector64.IN2
data[7] => Selector63.IN2
data[8] => Selector62.IN2
data[9] => Selector61.IN2
data[10] => Selector60.IN2
data[11] => Selector59.IN2
data[12] => Selector58.IN2
data[13] => Selector57.IN2
data[14] => Selector56.IN2
data[15] => Selector55.IN2
data[16] => Selector54.IN2
data[17] => Selector53.IN2
data[18] => Selector52.IN2
data[19] => Selector51.IN2
data[20] => Selector50.IN2
data[21] => Selector49.IN2
data[22] => Selector48.IN2
data[23] => Selector47.IN2
data[24] => Selector46.IN2
data[25] => Selector45.IN2
data[26] => Selector44.IN2
data[27] => Selector43.IN2
data[28] => Selector42.IN2
data[29] => Selector41.IN2
data[30] => Selector40.IN2
data[31] => Selector39.IN2
CH451_DCLK <= CH451_DCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
CH451_DIN <= CH451_DIN~reg0.DB_MAX_OUTPUT_PORT_TYPE
CH451_LOAD <= CH451_LOAD~reg0.DB_MAX_OUTPUT_PORT_TYPE