max3490.map.qmsg

来自「用VERILOG语言写的RS485通信程序,经调试可以直接使用」· QMSG 代码 · 共 47 行 · 第 1/3 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232tx rs232tx:m2 " "Info: Elaborating entity \"rs232tx\" for hierarchy \"rs232tx:m2\"" {  } { { "MAX3490.v" "m2" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 169 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock_gen_select.v 1 1 " "Warning: Using design file clock_gen_select.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 clock_gen_select " "Info: Found entity 1: clock_gen_select" {  } { { "clock_gen_select.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/clock_gen_select.v" 117 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_gen_select clock_gen_select:m3 " "Info: Elaborating entity \"clock_gen_select\" for hierarchy \"clock_gen_select:m3\"" {  } { { "MAX3490.v" "m3" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 177 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DIFF_ONLY_IN_CASE" "CH451_DISPLAY CH451_Display DISPLAY.v(32) " "Info (10281): Verilog HDL Declaration information at DISPLAY.v(32): object \"CH451_DISPLAY\" differs only in case from object \"CH451_Display\" in the same scope" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 32 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "CH451_Display DISPLAY.v(42) " "Info (10151): Verilog HDL Declaration information at DISPLAY.v(42): \"CH451_Display\" is declared here" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 42 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "DISPLAY.v 1 1 " "Warning: Using design file DISPLAY.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY " "Info: Found entity 1: DISPLAY" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DISPLAY DISPLAY:m4 " "Info: Elaborating entity \"DISPLAY\" for hierarchy \"DISPLAY:m4\"" {  } { { "MAX3490.v" "m4" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 186 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clock_gen_select:m3\|dds_phase\[1\] data_in GND " "Warning: Reduced register \"clock_gen_select:m3\|dds_phase\[1\]\" with stuck data_in port to stuck value GND" {  } { { "clock_gen_select.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/clock_gen_select.v" 209 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clock_gen_select:m3\|dds_phase\[0\] data_in GND " "Warning: Reduced register \"clock_gen_select:m3\|dds_phase\[0\]\" with stuck data_in port to stuck value GND" {  } { { "clock_gen_select.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/clock_gen_select.v" 209 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "rs232tx:m2\|q\[9\] High " "Info: Power-up level of register \"rs232tx:m2\|q\[9\]\" is not specified -- using power-up level of High to minimize register" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs232tx:m2\|q\[9\] data_in VCC " "Warning: Reduced register \"rs232tx:m2\|q\[9\]\" with stuck data_in port to stuck value VCC" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 170 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|MAX3490\|state 6 " "Info: State machine \"\|MAX3490\|state\" contains 6 states" {  } { { "MAX3490.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/MAX3490.v" 47 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|MAX3490\|DISPLAY:m4\|state 9 " "Info: State machine \"\|MAX3490\|DISPLAY:m4\|state\" contains 9 states" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 76 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|MAX3490\|DISPLAY:m4\|shift_state 7 " "Info: State machine \"\|MAX3490\|DISPLAY:m4\|shift_state\" contains 7 states" {  } { { "DISPLAY.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/DISPLAY.v" 77 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|MAX3490\|rs232tx:m2\|m1_state 4 " "Info: State machine \"\|MAX3490\|rs232tx:m2\|m1_state\" contains 4 states" {  } { { "rs232tx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232tx.v" 76 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|MAX3490\|rs232rx:m1\|m1_state 6 " "Info: State machine \"\|MAX3490\|rs232rx:m1\|m1_state\" contains 6 states" {  } { { "rs232rx.v" "" { Text "C:/Documents and Settings/jaylee/桌面/Logic design/RS485/rs232rx.v" 89 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}