statemachine.v

来自「典型的状态机」· Verilog 代码 · 共 75 行

// simple state machine
//
// look at input token, if token=9 then the next token seen is to be
// assigned to the output out on posedge of clk (for one clk cycle only)  
// and a count of the number of nines seen is to be output on count
//  (posedge clk)

`define waitfornine 2'b01
`define foundnine 2'b10

module statemachine(out, count, token, reset,clk);
   input reset,clk;
   input [4:0] token;
   output [4:0] out,count;

   reg [1:0]    state,nextstate;
   reg [4:0]    out,nextout;
   reg [4:0]    count,nextcount;
   

   // sequential logic
   always @(posedge clk) begin
      if(reset) begin
         state <=`waitfornine;
         count <=0;
         out   <=0;
      end // if (reset)
      else begin
         state <=nextstate;
         count <=nextcount;
         out   <=nextout;
      end // else: !if(reset)
   end // always @ (posedge clk)


   // combinational logic  ----
   // all values that are assigned or change the flow of logic
   //  must be in the sensitivity list
   always @(token or state or count) begin 
      //  all outputs must be assign to  in all branches of the logic,
      //  or latches will be inferred (latches are bad).
      case(state)
        `waitfornine: begin
           nextout=0;
           if(token==9) begin 
              nextstate=`foundnine;
              nextcount=count+1; 
           end // if (token==9)
           else begin
              nextstate=`waitfornine;
              nextcount=count;
           end // else: !if(token==9)
        end // case: `waitfornine
        `foundnine: begin
           nextout=token;
           if(token==9) begin 
              nextstate=`foundnine;
              nextcount=count+1;
           end // if (token==9)
           else begin
              nextstate=`waitfornine;
              nextcount=count;
           end // else: !if(token==9)
        end // case: `foundnine
        default: begin  // a default is needed by the synthesis tool
           nextout = out; // to ensure that no latches are generated.
           nextstate = state;
           nextcount = count;
        end // case: default
      endcase // case(state)
   end // always (token or state)

endmodule // statemachine