recver.vhd

一种基于VHDL的uart算法的实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity recver is
port(reset: in std_logic;
       clk: in std_logic;
         rden: in std_logic;
           rxd: in std_logic;
      dout: out std_logic_vector(7 downto 0);
         rd_flag: out std_logic;
            frame_error :out std_logic;
               parity_error: out std_logic);
end recver;
architecture behav of recver is
signal rx_temp1 : std_logic;
signal rx_temp2 : std_logic;
signal band_ce  : std_logic;
signal clkdiv   : unsigned(3 downto 0);
signal shift_reg : std_logic_vector(7 downto 0);
signal dout_buf  : std_logic_vector(7 downto 0);
signal rec_count : std_logic_vector(3 downto 0);
signal band_clk  : std_logic;
signal parity    : std_logic;
begin
p1:process(reset,clk)
begin
if(reset='1')then rx_temp1<='1';
  rx_temp2<='1';
  elsif(clk'event and clk='1')then 
    rx_temp1<=rxd;
      rx_temp2<=rx_temp1;
  end if;
  end process;
p2:process(reset,clk)
    begin
    if(reset='1')or(rec_count="1010") then band_ce<='0';
        elsif(clk'event and clk='1')then
            if((rx_temp1='0')and(rx_temp2='1'))then band_ce<='1';
                  end if;
                    end if;
                      end process;
p3:process(band_clk,reset)
variable parity_reg : std_logic;
begin
if(reset='1')then shift_reg<="00000000";
  dout_buf<="00000000";
  frame_error<='0';
  parity<='0';
  elsif(rec_count<="1001")and(rec_count>="0001") then
   shift_reg(0)<=rx_temp2;
   shift_reg(7 downto 0)<=shift_reg(6 downto 0)&'0';
    elsif(rec_count="1010")then 
    parity_reg:=((shift_reg(0))xor(shift_reg(1))xor(shift_reg(2))xor(shift_reg(3))
                    xor(shift_reg(4))xor(shift_reg(5))xor(shift_reg(6))xor(shift_reg(7)));
          dout_buf<=shift_reg;
          parity_reg:=rx_temp2;
          if(parity_reg=rx_temp2)then
             parity_error<='0';
              else parity_error<='1';
                    end if;
    end if;
    end process;
p4:process(clk,reset,band_ce)
  begin
   if(reset='1')or(rec_count="1100"and band_ce='0')then rec_count<="0000";
     elsif(band_ce='1')then rec_count<=rec_count+"0001";
                end if;
           
end process;
p5:process(clk)
  variable cnt : integer:=0;
  begin
  if(cnt<8)then cnt:=cnt+1;
      band_clk<='0';
     elsif((cnt>=8)and(cnt<=15))then band_clk<='1';
          cnt:=cnt+1;
       elsif(cnt>15)then cnt:=0;
       end if;
  end process;
 p6: process(reset,rden,band_ce,parity)
  begin
  if(reset='1')or(rden='0')then rd_flag<='0';
                   elsif(band_ce='0' and parity='0')then rd_flag<='1';
                   
                      end if;
           end process;
p7:process(rden,band_clk)
    begin
    if(band_clk'event and band_clk='1')then
     if(rden='0')then dout<="ZZZZZZZZ";
       else dout<=dout_buf;
       end if;
         else null;
         end if;
         end process;
           
 end behav;