top.vhd

一种基于VHDL的uart算法的实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity top is
port(din:in std_logic_vector(7 downto 0);
      rden:in std_logic;
       wren:in std_logic;
         clk:in std_logic;
           reset:in std_logic;
             rxd:in std_logic;
      dout:out std_logic_vector(7 downto 0);
        frame_error:out std_logic;
           txd : out std_logic;
              rd_flag:out std_logic;
                sent_flag : out std_logic;
                parity_error : out std_logic;
                wr_flag:out std_logic);
end top;
architecture sys of top is
component fz
port(clk:in std_logic;
      clk_out:out std_logic);
end component;
component recver
port(reset: in std_logic;
       clk: in std_logic;
         rden: in std_logic;
           rxd: in std_logic;
      dout: out std_logic_vector(7 downto 0);
         rd_flag: out std_logic;
            frame_error :out std_logic;
               parity_error: out std_logic);
    end component;
component transmiter
port(din :in std_logic_vector(7 downto 0);
     reset : in std_logic;
     clk   : in std_logic;
     wren  : in std_logic;
     sent_flag: out std_logic;
     wr_flag: out std_logic;
     txd   : out std_logic);
end component;
signal clk_sys: std_logic;
begin
com:fz port map(clk=>clk,clk_out=>clk_sys);
com1:recver port map(reset=>reset,clk=>clk_sys,rden=>rden,rxd=>rxd,dout=>dout,
                       rd_flag=>rd_flag,frame_error=>frame_error,parity_error=>parity_error
                         );
com2:transmiter port map(din=>din,reset=>reset,clk=>clk_sys,wren=>wren,sent_flag=sent_flag,
                          wr_flag=>wr_flag,txd=>txd);
     end sys;