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一种基于VHDL的uart算法的实现

Analysis & Synthesis Status : Failed - Wed Jun 20 13:05:57 2012
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
Revision Name : top
Top-level Entity Name : top
Family : Stratix II
Logic utilization : N/A until Partition Merge
    Combinational ALUTs : N/A until Partition Merge
    Dedicated logic registers : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge