transmiter.vhd

一种基于VHDL的uart算法的实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity transmiter is
port(din :in std_logic_vector(7 downto 0);
     reset : in std_logic;
     clk   : in std_logic;
     wren  : in std_logic;
     sent_flag: out std_logic;
     wr_flag: out std_logic;
     txd   : out std_logic);
       end transmiter;
architecture behav of transmiter is
signal band_ce : std_logic;
signal shift_reg :std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(7 downto 0);

signal band_clk :std_logic;
signal sent_count : std_logic_vector(3 downto 0);
signal wr_temp1  : std_logic;
signal wr_temp2  : std_logic;
begin 
p1: process(clk,reset)
    begin
    if(reset='1')then wr_temp1<='1';
                      wr_temp2<='1';
          elsif(clk'event and clk='1')then
               wr_temp1<=wren;
               wr_temp2<=wr_temp1;
                   end if;
    end process;
p2:process(clk)
   variable clkdiv : integer;
   begin
   if(clk'event and clk='1')then
      if(clkdiv<=7)then clkdiv:=clkdiv+1;
         band_clk<='0';
           elsif(clkdiv<=15)then band_clk<='1';
                clkdiv:=clkdiv+1;
                   end if;
                     end if;
   end process;
     
p3:process(clk,reset,sent_count)
    begin
    if(reset='1')then band_ce<='0';
           sent_flag<='0';
              elsif(clk'event and clk='1')then
                   if((wr_temp1='0')and(wr_temp2='1')) then band_ce<='1';
                               sent_flag<='0';
                         elsif(sent_count="0010")then sent_flag<='1';
                          elsif(sent_count="1010")then sent_flag<='0';
                            elsif(sent_count="1110")then band_ce<='0';
                                  end if;
                                     end if;
     end process;
  p4:process(reset,wren)
     begin
     if(reset='1')then data_buf<=(OTHERS=>'0');
            elsif(wren'event and wren='0')then data_buf<=din;
                      end if;
                        end process;
p5:process(band_clk,reset)
   variable parity_temp: std_logic;
    begin
    if(reset='1')then txd<='1';
         wr_flag<='1';
         shift_reg<="00000000";
           elsif(band_clk'event and band_clk='1')then
                 if(sent_count="0001")then shift_reg<=data_buf;
                      elsif(sent_count="0010")then txd<='0';
                        elsif((sent_count="0011")and(sent_count<="1010"))then 
                                 shift_reg(7 downto 0)<=shift_reg(6 downto 0)&'0';
                                       txd<=shift_reg(7);
                             parity_temp:=parity_temp xor shift_reg(7);
                                  elsif(sent_count="1011")then txd<=parity_temp;
                                    elsif(sent_count="1100")then txd<='1';
                                    end if;
     end if;
 end process;
 p6:process(reset,band_clk)
    begin
     if(reset='1'or band_ce='0')then sent_count<="0000";
         elsif(band_clk'event and band_clk='1')then
                   if(sent_count<=1100)then 
                         if(band_ce='1')then sent_count<=sent_count+'1';
                                    else sent_count<="0000";
                                          end if;
                     end if;
      end if;
      end process;
      end behav;